From: Saeed Mahameed <saeedm@mellanox.com>
To: "David S. Miller" <davem@davemloft.net>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
Tariq Toukan <tariqt@mellanox.com>,
Eran Ben Elisha <eranbe@mellanox.com>,
Saeed Mahameed <saeedm@mellanox.com>
Subject: [net-next 06/14] net/mlx5: Accel, Add core TLS support for the Connect-X family
Date: Thu, 4 Jul 2019 18:15:57 +0000 [thread overview]
Message-ID: <20190704181235.8966-7-saeedm@mellanox.com> (raw)
In-Reply-To: <20190704181235.8966-1-saeedm@mellanox.com>
From: Tariq Toukan <tariqt@mellanox.com>
Add support for the new TLS implementation of the Connect-X family.
Introduce a new compilation flag MLX5_TLS for it.
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
.../net/ethernet/mellanox/mlx5/core/Kconfig | 13 ++++-
.../ethernet/mellanox/mlx5/core/accel/tls.c | 42 +++++++++++++++-
.../ethernet/mellanox/mlx5/core/accel/tls.h | 49 ++++++++++++++++++-
3 files changed, 101 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/Kconfig b/drivers/net/ethernet/mellanox/mlx5/core/Kconfig
index 6556490d809c..37fef8cd25e3 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/Kconfig
+++ b/drivers/net/ethernet/mellanox/mlx5/core/Kconfig
@@ -134,10 +134,21 @@ config MLX5_FPGA_TLS
mlx5_core driver will include the Innova FPGA core and allow building
sandbox-specific client drivers.
+config MLX5_TLS
+ bool "Mellanox Technologies TLS Connect-X support"
+ depends on MLX5_CORE_EN
+ depends on TLS_DEVICE
+ depends on TLS=y || MLX5_CORE=m
+ select MLX5_ACCEL
+ default n
+ help
+ Build TLS support for the Connect-X family of network cards by Mellanox
+ Technologies.
+
config MLX5_EN_TLS
bool "TLS cryptography-offload accelaration"
depends on MLX5_CORE_EN
- depends on MLX5_FPGA_TLS
+ depends on MLX5_FPGA_TLS || MLX5_TLS
default y
help
Build support for TLS cryptography-offload accelaration in the NIC.
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c b/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c
index a2c9eda1ebf5..cab708af3422 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.c
@@ -35,6 +35,7 @@
#include "accel/tls.h"
#include "mlx5_core.h"
+#include "lib/mlx5.h"
#ifdef CONFIG_MLX5_FPGA_TLS
#include "fpga/tls.h"
@@ -63,7 +64,8 @@ int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle, u32 seq,
bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)
{
- return mlx5_fpga_is_tls_device(mdev);
+ return mlx5_fpga_is_tls_device(mdev) ||
+ mlx5_accel_is_ktls_device(mdev);
}
u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev)
@@ -81,3 +83,41 @@ void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev)
mlx5_fpga_tls_cleanup(mdev);
}
#endif
+
+#ifdef CONFIG_MLX5_TLS
+int mlx5_ktls_create_key(struct mlx5_core_dev *mdev,
+ struct tls_crypto_info *crypto_info,
+ u32 *p_key_id)
+{
+ u32 sz_bytes;
+ void *key;
+
+ switch (crypto_info->cipher_type) {
+ case TLS_CIPHER_AES_GCM_128: {
+ struct tls12_crypto_info_aes_gcm_128 *info =
+ (struct tls12_crypto_info_aes_gcm_128 *)crypto_info;
+
+ key = info->key;
+ sz_bytes = sizeof(info->key);
+ break;
+ }
+ case TLS_CIPHER_AES_GCM_256: {
+ struct tls12_crypto_info_aes_gcm_256 *info =
+ (struct tls12_crypto_info_aes_gcm_256 *)crypto_info;
+
+ key = info->key;
+ sz_bytes = sizeof(info->key);
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
+
+ return mlx5_create_encryption_key(mdev, key, sz_bytes, p_key_id);
+}
+
+void mlx5_ktls_destroy_key(struct mlx5_core_dev *mdev, u32 key_id)
+{
+ mlx5_destroy_encryption_key(mdev, key_id);
+}
+#endif
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h b/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h
index e5d306ad7f91..879321b21616 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h
@@ -37,6 +37,50 @@
#include <linux/mlx5/driver.h>
#include <linux/tls.h>
+#ifdef CONFIG_MLX5_TLS
+int mlx5_ktls_create_key(struct mlx5_core_dev *mdev,
+ struct tls_crypto_info *crypto_info,
+ u32 *p_key_id);
+void mlx5_ktls_destroy_key(struct mlx5_core_dev *mdev, u32 key_id);
+
+static inline bool mlx5_accel_is_ktls_device(struct mlx5_core_dev *mdev)
+{
+ if (!MLX5_CAP_GEN(mdev, tls))
+ return false;
+
+ if (!MLX5_CAP_GEN(mdev, log_max_dek))
+ return false;
+
+ return MLX5_CAP_TLS(mdev, tls_1_2_aes_gcm_128);
+}
+
+static inline bool mlx5e_ktls_type_check(struct mlx5_core_dev *mdev,
+ struct tls_crypto_info *crypto_info)
+{
+ switch (crypto_info->cipher_type) {
+ case TLS_CIPHER_AES_GCM_128:
+ if (crypto_info->version == TLS_1_2_VERSION)
+ return MLX5_CAP_TLS(mdev, tls_1_2_aes_gcm_128);
+ break;
+ }
+
+ return false;
+}
+#else
+static inline int
+mlx5_ktls_create_key(struct mlx5_core_dev *mdev,
+ struct tls_crypto_info *crypto_info,
+ u32 *p_key_id) { return -ENOTSUPP; }
+static inline void
+mlx5_ktls_destroy_key(struct mlx5_core_dev *mdev, u32 key_id) {}
+
+static inline bool
+mlx5_accel_is_ktls_device(struct mlx5_core_dev *mdev) { return false; }
+static inline bool
+mlx5e_ktls_type_check(struct mlx5_core_dev *mdev,
+ struct tls_crypto_info *crypto_info) { return false; }
+#endif
+
#ifdef CONFIG_MLX5_FPGA_TLS
enum {
MLX5_ACCEL_TLS_TX = BIT(0),
@@ -83,7 +127,10 @@ static inline void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
bool direction_sx) { }
static inline int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle,
u32 seq, u64 rcd_sn) { return 0; }
-static inline bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev) { return false; }
+static inline bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)
+{
+ return mlx5_accel_is_ktls_device(mdev);
+}
static inline u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev) { return 0; }
static inline int mlx5_accel_tls_init(struct mlx5_core_dev *mdev) { return 0; }
static inline void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev) { }
--
2.21.0
next prev parent reply other threads:[~2019-07-04 18:16 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-04 18:15 [pull request][net-next 00/14] Mellanox, mlx5 updates 2019-07-04 Saeed Mahameed
2019-07-04 18:15 ` [net-next 01/14] net/mlx5: Added fw version query command Saeed Mahameed
2019-07-04 18:15 ` [net-next 02/14] net/mlx5: Added devlink info callback Saeed Mahameed
2019-07-04 18:15 ` [net-next 03/14] net/mlx5: Accel, Expose accel wrapper for IPsec FPGA function Saeed Mahameed
2019-07-04 18:15 ` [net-next 04/14] net/mlx5: Kconfig, Better organize compilation flags Saeed Mahameed
2019-07-04 18:15 ` [net-next 05/14] net/mlx5: Add crypto library to support create/destroy encryption key Saeed Mahameed
2019-07-04 20:50 ` Jakub Kicinski
2019-07-04 18:15 ` Saeed Mahameed [this message]
2019-07-04 18:15 ` [net-next 07/14] net/mlx5e: Move helper functions to a new txrx datapath header Saeed Mahameed
2019-07-04 18:16 ` [net-next 08/14] net/mlx5e: Tx, Enforce L4 inline copy when needed Saeed Mahameed
2019-07-04 18:16 ` [net-next 09/14] net/mlx5e: Tx, Make SQ WQE fetch function type generic Saeed Mahameed
2019-07-04 18:16 ` [net-next 10/14] net/mlx5e: Tx, Don't implicitly assume SKB-less wqe has one WQEBB Saeed Mahameed
2019-07-04 18:16 ` [net-next 11/14] net/mlx5e: Tx, Unconstify SQ stop room Saeed Mahameed
2019-07-04 18:16 ` [net-next 12/14] net/mlx5e: Re-work TIS creation functions Saeed Mahameed
2019-07-04 18:16 ` [net-next 13/14] net/mlx5e: Introduce a fenced NOP WQE posting function Saeed Mahameed
2019-07-04 18:16 ` [net-next 14/14] net/mlx5e: Add kTLS TX HW offload support Saeed Mahameed
2019-07-04 20:12 ` Jakub Kicinski
2019-07-04 20:30 ` Saeed Mahameed
2019-07-04 20:45 ` Jakub Kicinski
2019-07-05 14:31 ` Tariq Toukan
2019-07-05 19:43 ` Jakub Kicinski
2019-07-04 21:35 ` Jakub Kicinski
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