From: Saeed Mahameed <saeedm@mellanox.com>
To: "David S. Miller" <davem@davemloft.net>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
Aya Levin <ayal@mellanox.com>, Moshe Shemesh <moshe@mellanox.com>,
Saeed Mahameed <saeedm@mellanox.com>
Subject: [net-next 13/14] net/mlx5: Expose HW capability bits for port buffer per priority congestion counters
Date: Thu, 5 Sep 2019 21:51:18 +0000 [thread overview]
Message-ID: <20190905215034.22713-14-saeedm@mellanox.com> (raw)
In-Reply-To: <20190905215034.22713-1-saeedm@mellanox.com>
From: Aya Levin <ayal@mellanox.com>
Map capability bit indicating that HCA supports port buffer's congestion
counters. Also map registers with the corresponding counters.
Signed-off-by: Aya Levin <ayal@mellanox.com>
Reviewed-by: Moshe Shemesh <moshe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
include/linux/mlx5/device.h | 1 +
include/linux/mlx5/mlx5_ifc.h | 29 ++++++++++++++++++++++++-----
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 8dd081051a79..f3773e8536bb 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -1316,6 +1316,7 @@ enum {
MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
+ MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
};
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 7d65c0578ac9..a487b681b516 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1196,7 +1196,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 rts2rts_qp_counters_set_id[0x1];
u8 reserved_at_16a[0x2];
u8 vnic_env_int_rq_oob[0x1];
- u8 reserved_at_16d[0x2];
+ u8 sbcam_reg[0x1];
+ u8 reserved_at_16e[0x1];
u8 qcam_reg[0x1];
u8 gid_table_size[0x10];
@@ -1960,12 +1961,28 @@ struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
u8 port_xmit_wait[0x20];
};
-struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
+struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
u8 transmit_queue_high[0x20];
u8 transmit_queue_low[0x20];
- u8 reserved_at_40[0x780];
+ u8 no_buffer_discard_uc_high[0x20];
+
+ u8 no_buffer_discard_uc_low[0x20];
+
+ u8 reserved_at_80[0x740];
+};
+
+struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
+ u8 wred_discard_high[0x20];
+
+ u8 wred_discard_low[0x20];
+
+ u8 ecn_marked_tc_high[0x20];
+
+ u8 ecn_marked_tc_low[0x20];
+
+ u8 reserved_at_80[0x740];
};
struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
@@ -3642,7 +3659,8 @@ union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
- struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
+ struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
+ struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
@@ -9422,7 +9440,8 @@ union mlx5_ifc_ports_control_registers_document_bits {
struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
- struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
+ struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
+ struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
struct mlx5_ifc_pamp_reg_bits pamp_reg;
struct mlx5_ifc_paos_reg_bits paos_reg;
--
2.21.0
next prev parent reply other threads:[~2019-09-05 21:51 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-05 21:50 [pull request][net-next 00/14] Mellanox, mlx5 cleanups & port congestion stats Saeed Mahameed
2019-09-05 21:50 ` [net-next 01/14] net/mlx5e: Fix static checker warning of potential pointer math issue Saeed Mahameed
2019-09-05 21:50 ` [net-next 02/14] net/mlx5: Kconfig: Fix MLX5_CORE dependency with PCI_HYPERV_INTERFACE Saeed Mahameed
2019-09-05 21:50 ` [net-next 03/14] net/mlx5e: Use ipv6_stub to avoid dependency with ipv6 being a module Saeed Mahameed
2019-09-05 21:51 ` [net-next 04/14] net/mlx5e: Remove leftover declaration Saeed Mahameed
2019-09-05 21:51 ` [net-next 05/14] net/mlx5: fix spelling mistake "offlaods" -> "offloads" Saeed Mahameed
2019-09-05 21:51 ` [net-next 06/14] net/mlx5: fix missing assignment of variable err Saeed Mahameed
2019-09-05 21:51 ` [net-next 07/14] net/mlx5: Use PTR_ERR_OR_ZERO rather than its implementation Saeed Mahameed
2019-09-05 21:51 ` [net-next 08/14] net/mlx5e: kTLS, Remove unused function parameter Saeed Mahameed
2019-09-05 21:51 ` [net-next 09/14] net/mlx5e: Remove unnecessary clear_bit()s Saeed Mahameed
2019-09-05 21:51 ` [net-next 10/14] net/mlx5: DR, Remove useless set memory to zero use memset() Saeed Mahameed
2019-09-05 21:51 ` [net-next 11/14] net/mlx5: DR, Fix error return code in dr_domain_init_resources() Saeed Mahameed
2019-09-05 21:51 ` [net-next 12/14] net/mlx5: DR, Remove redundant dev_name print from err log Saeed Mahameed
2019-09-05 21:51 ` Saeed Mahameed [this message]
2019-09-05 21:51 ` [net-next 14/14] net/mlx5e: Add port buffer's congestion counters Saeed Mahameed
2019-09-07 15:40 ` [pull request][net-next 00/14] Mellanox, mlx5 cleanups & port congestion stats David Miller
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