[patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes

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* [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes
@ 2019-10-12 16:27 Jiri Pirko
  2019-10-12 16:27 ` [patch net-next v2 1/2] ethtool: " Jiri Pirko
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Jiri Pirko @ 2019-10-12 16:27 UTC (permalink / raw)
  To: netdev; +Cc: davem, jakub.kicinski, andrew, f.fainelli, hkallweit1, mlxsw

From: Jiri Pirko <jiri@mellanox.com>

Add 400Gbps bits to ethtool and introduce support in mlxsw. These modes
are supported by the Spectrum-2 switch ASIC.

Jiri Pirko (2):
  ethtool: Add support for 400Gbps (50Gbps per lane) link modes
  mlxsw: spectrum: Add support for 400Gbps (50Gbps per lane) link modes

 drivers/net/ethernet/mellanox/mlxsw/reg.h     |  1 +
 .../net/ethernet/mellanox/mlxsw/spectrum.c    | 52 +++++++++++++++----
 drivers/net/phy/phy-core.c                    | 10 +++-
 include/uapi/linux/ethtool.h                  |  6 +++
 4 files changed, 58 insertions(+), 11 deletions(-)

-- 
2.21.0


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [patch net-next v2 1/2] ethtool: Add support for 400Gbps (50Gbps per lane) link modes
  2019-10-12 16:27 [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes Jiri Pirko
@ 2019-10-12 16:27 ` Jiri Pirko
  2019-10-12 16:27 ` [patch net-next v2 2/2] mlxsw: spectrum: " Jiri Pirko
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 7+ messages in thread
From: Jiri Pirko @ 2019-10-12 16:27 UTC (permalink / raw)
  To: netdev; +Cc: davem, jakub.kicinski, andrew, f.fainelli, hkallweit1, mlxsw

From: Jiri Pirko <jiri@mellanox.com>

Add support for 400Gbps speed, link modes of 50Gbps per lane

Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
---
v1->v2:
- added patch description
---
 drivers/net/phy/phy-core.c   | 10 +++++++++-
 include/uapi/linux/ethtool.h |  6 ++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 9412669b579c..4d96f7a8e8f2 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -8,7 +8,7 @@
 
 const char *phy_speed_to_str(int speed)
 {
-	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 69,
+	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 74,
 		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
 		"If a speed or mode has been added please update phy_speed_to_str "
 		"and the PHY settings array.\n");
@@ -42,6 +42,8 @@ const char *phy_speed_to_str(int speed)
 		return "100Gbps";
 	case SPEED_200000:
 		return "200Gbps";
+	case SPEED_400000:
+		return "400Gbps";
 	case SPEED_UNKNOWN:
 		return "Unknown";
 	default:
@@ -70,6 +72,12 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str);
 			       .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
 
 static const struct phy_setting settings[] = {
+	/* 400G */
+	PHY_SETTING( 400000, FULL, 400000baseCR8_Full		),
+	PHY_SETTING( 400000, FULL, 400000baseKR8_Full		),
+	PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full	),
+	PHY_SETTING( 400000, FULL, 400000baseDR8_Full		),
+	PHY_SETTING( 400000, FULL, 400000baseSR8_Full		),
 	/* 200G */
 	PHY_SETTING( 200000, FULL, 200000baseCR4_Full		),
 	PHY_SETTING( 200000, FULL, 200000baseKR4_Full		),
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 8938b76c4ee3..d4591792f0b4 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1507,6 +1507,11 @@ enum ethtool_link_mode_bit_indices {
 	ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT	 = 66,
 	ETHTOOL_LINK_MODE_100baseT1_Full_BIT		 = 67,
 	ETHTOOL_LINK_MODE_1000baseT1_Full_BIT		 = 68,
+	ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT	 = 69,
+	ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT	 = 70,
+	ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,
+	ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT	 = 72,
+	ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT	 = 73,
 
 	/* must be last entry */
 	__ETHTOOL_LINK_MODE_MASK_NBITS
@@ -1618,6 +1623,7 @@ enum ethtool_link_mode_bit_indices {
 #define SPEED_56000		56000
 #define SPEED_100000		100000
 #define SPEED_200000		200000
+#define SPEED_400000		400000
 
 #define SPEED_UNKNOWN		-1
 
-- 
2.21.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [patch net-next v2 2/2] mlxsw: spectrum: Add support for 400Gbps (50Gbps per lane) link modes
  2019-10-12 16:27 [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes Jiri Pirko
  2019-10-12 16:27 ` [patch net-next v2 1/2] ethtool: " Jiri Pirko
@ 2019-10-12 16:27 ` Jiri Pirko
  2019-10-15 19:07 ` [patch net-next v2 0/2] mlxsw: " Jakub Kicinski
  2019-10-15 22:03 ` David Miller
  3 siblings, 0 replies; 7+ messages in thread
From: Jiri Pirko @ 2019-10-12 16:27 UTC (permalink / raw)
  To: netdev; +Cc: davem, jakub.kicinski, andrew, f.fainelli, hkallweit1, mlxsw

From: Jiri Pirko <jiri@mellanox.com>

Extend speed support with 400Gbps

Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
---
 drivers/net/ethernet/mellanox/mlxsw/reg.h     |  1 +
 .../net/ethernet/mellanox/mlxsw/spectrum.c    | 52 +++++++++++++++----
 2 files changed, 43 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index 7b538e698a3d..f5e39758c6ac 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -4111,6 +4111,7 @@ MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4		BIT(9)
 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)
 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)
+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8				BIT(15)
 
 /* reg_ptys_ext_eth_proto_cap
  * Extended Ethernet port supported speeds and protocols.
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
index 3c5154e559b2..ae3c4da11520 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
@@ -2912,9 +2912,22 @@ mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
 
+static const enum ethtool_link_mode_bit_indices
+mlxsw_sp2_mask_ethtool_400gaui_8[] = {
+	ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
+	ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
+	ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
+	ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
+	ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
+};
+
+#define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \
+	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)
+
 #define MLXSW_SP_PORT_MASK_WIDTH_1X	BIT(0)
 #define MLXSW_SP_PORT_MASK_WIDTH_2X	BIT(1)
 #define MLXSW_SP_PORT_MASK_WIDTH_4X	BIT(2)
+#define MLXSW_SP_PORT_MASK_WIDTH_8X	BIT(3)
 
 static u8 mlxsw_sp_port_mask_width_get(u8 width)
 {
@@ -2925,6 +2938,8 @@ static u8 mlxsw_sp_port_mask_width_get(u8 width)
 		return MLXSW_SP_PORT_MASK_WIDTH_2X;
 	case 4:
 		return MLXSW_SP_PORT_MASK_WIDTH_4X;
+	case 8:
+		return MLXSW_SP_PORT_MASK_WIDTH_8X;
 	default:
 		WARN_ON_ONCE(1);
 		return 0;
@@ -2946,7 +2961,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
-				  MLXSW_SP_PORT_MASK_WIDTH_4X,
+				  MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_100,
 	},
 	{
@@ -2955,7 +2971,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
-				  MLXSW_SP_PORT_MASK_WIDTH_4X,
+				  MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_1000,
 	},
 	{
@@ -2964,7 +2981,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
-				  MLXSW_SP_PORT_MASK_WIDTH_4X,
+				  MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_2500,
 	},
 	{
@@ -2973,7 +2991,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
-				  MLXSW_SP_PORT_MASK_WIDTH_4X,
+				  MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_5000,
 	},
 	{
@@ -2982,14 +3001,16 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
-				  MLXSW_SP_PORT_MASK_WIDTH_4X,
+				  MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_10000,
 	},
 	{
 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
-		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,
+		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_40000,
 	},
 	{
@@ -2998,7 +3019,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
-				  MLXSW_SP_PORT_MASK_WIDTH_4X,
+				  MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_25000,
 	},
 	{
@@ -3006,7 +3028,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_2X |
-				  MLXSW_SP_PORT_MASK_WIDTH_4X,
+				  MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_50000,
 	},
 	{
@@ -3020,7 +3043,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
-		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,
+		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_100000,
 	},
 	{
@@ -3034,9 +3058,17 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
-		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,
+		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X |
+				  MLXSW_SP_PORT_MASK_WIDTH_8X,
 		.speed		= SPEED_200000,
 	},
+	{
+		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8,
+		.mask_ethtool	= mlxsw_sp2_mask_ethtool_400gaui_8,
+		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN,
+		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_8X,
+		.speed		= SPEED_400000,
+	},
 };
 
 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
-- 
2.21.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes
  2019-10-12 16:27 [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes Jiri Pirko
  2019-10-12 16:27 ` [patch net-next v2 1/2] ethtool: " Jiri Pirko
  2019-10-12 16:27 ` [patch net-next v2 2/2] mlxsw: spectrum: " Jiri Pirko
@ 2019-10-15 19:07 ` Jakub Kicinski
  2019-10-15 20:14   ` Jiri Pirko
  2019-10-15 22:03 ` David Miller
  3 siblings, 1 reply; 7+ messages in thread
From: Jakub Kicinski @ 2019-10-15 19:07 UTC (permalink / raw)
  To: Jiri Pirko; +Cc: netdev, davem, andrew, f.fainelli, hkallweit1, mlxsw

On Sat, 12 Oct 2019 18:27:56 +0200, Jiri Pirko wrote:
> From: Jiri Pirko <jiri@mellanox.com>
> 
> Add 400Gbps bits to ethtool and introduce support in mlxsw. These modes
> are supported by the Spectrum-2 switch ASIC.

Thanks for the update, looks good to me!

Out of curiosity - why did we start bunching up LR, ER and FR?

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes
  2019-10-15 19:07 ` [patch net-next v2 0/2] mlxsw: " Jakub Kicinski
@ 2019-10-15 20:14   ` Jiri Pirko
  2019-10-15 20:45     ` Jakub Kicinski
  0 siblings, 1 reply; 7+ messages in thread
From: Jiri Pirko @ 2019-10-15 20:14 UTC (permalink / raw)
  To: Jakub Kicinski; +Cc: netdev, davem, andrew, f.fainelli, hkallweit1, mlxsw

Tue, Oct 15, 2019 at 09:07:57PM CEST, jakub.kicinski@netronome.com wrote:
>On Sat, 12 Oct 2019 18:27:56 +0200, Jiri Pirko wrote:
>> From: Jiri Pirko <jiri@mellanox.com>
>> 
>> Add 400Gbps bits to ethtool and introduce support in mlxsw. These modes
>> are supported by the Spectrum-2 switch ASIC.
>
>Thanks for the update, looks good to me!
>
>Out of curiosity - why did we start bunching up LR, ER and FR?

No clue. But it's been done like that for other speeds too.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes
  2019-10-15 20:14   ` Jiri Pirko
@ 2019-10-15 20:45     ` Jakub Kicinski
  0 siblings, 0 replies; 7+ messages in thread
From: Jakub Kicinski @ 2019-10-15 20:45 UTC (permalink / raw)
  To: Jiri Pirko; +Cc: netdev, davem, andrew, f.fainelli, hkallweit1, mlxsw

On Tue, 15 Oct 2019 22:14:16 +0200, Jiri Pirko wrote:
> Tue, Oct 15, 2019 at 09:07:57PM CEST, jakub.kicinski@netronome.com wrote:
> >On Sat, 12 Oct 2019 18:27:56 +0200, Jiri Pirko wrote:  
> >> From: Jiri Pirko <jiri@mellanox.com>
> >> 
> >> Add 400Gbps bits to ethtool and introduce support in mlxsw. These modes
> >> are supported by the Spectrum-2 switch ASIC.  
> >
> >Thanks for the update, looks good to me!
> >
> >Out of curiosity - why did we start bunching up LR, ER and FR?  
> 
> No clue. But it's been done like that for other speeds too.

Looks like for 50G Serdeses and 4x25G we started grouping by Clause.
Probably makes sense.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes
  2019-10-12 16:27 [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes Jiri Pirko
                   ` (2 preceding siblings ...)
  2019-10-15 19:07 ` [patch net-next v2 0/2] mlxsw: " Jakub Kicinski
@ 2019-10-15 22:03 ` David Miller
  3 siblings, 0 replies; 7+ messages in thread
From: David Miller @ 2019-10-15 22:03 UTC (permalink / raw)
  To: jiri; +Cc: netdev, jakub.kicinski, andrew, f.fainelli, hkallweit1, mlxsw

From: Jiri Pirko <jiri@resnulli.us>
Date: Sat, 12 Oct 2019 18:27:56 +0200

> From: Jiri Pirko <jiri@mellanox.com>
> 
> Add 400Gbps bits to ethtool and introduce support in mlxsw. These modes
> are supported by the Spectrum-2 switch ASIC.

Series applied, thanks.

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2019-10-15 22:03 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-10-12 16:27 [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps per lane) link modes Jiri Pirko
2019-10-12 16:27 ` [patch net-next v2 1/2] ethtool: " Jiri Pirko
2019-10-12 16:27 ` [patch net-next v2 2/2] mlxsw: spectrum: " Jiri Pirko
2019-10-15 19:07 ` [patch net-next v2 0/2] mlxsw: " Jakub Kicinski
2019-10-15 20:14   ` Jiri Pirko
2019-10-15 20:45     ` Jakub Kicinski
2019-10-15 22:03 ` David Miller

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