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From: Adrian Bunk <bunk@kernel.org>
To: Dan Murphy <dmurphy@ti.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	netdev@vger.kernel.org
Subject: dp83867: Why does ti,fifo-depth set only TX, and why is it mandatory?
Date: Thu, 14 Nov 2019 18:24:32 +0200	[thread overview]
Message-ID: <20191114162431.GA21979@localhost> (raw)

Hi,

looking at the ti,fifo-depth property to set the TX FIFO Depth in the 
dp83867 driver I was wondering:

1. Why does it set only TX?
Is there a reason why TX needs setting but RX does not?
(RX FIFO Depth is SGMII-only, but that's what I am using)

2. Why is it a mandatory property?
Perhaps I am missing something obvious, but why can't the driver either
leave the value untouched or set the maximum when nothing is configured?

Thanks in advance
Adrian


             reply	other threads:[~2019-11-14 16:31 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-14 16:24 Adrian Bunk [this message]
2019-11-14 17:53 ` dp83867: Why does ti,fifo-depth set only TX, and why is it mandatory? Dan Murphy
2019-11-14 19:47   ` Adrian Bunk
2019-11-14 20:01     ` Dan Murphy
2019-11-19 17:35       ` Dan Murphy
2019-11-21 20:24       ` Dan Murphy
2019-11-23 21:00         ` Adrian Bunk

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