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From: Andrew Lunn <andrew@lunn.ch>
To: Marek Behun <marek.behun@nic.cz>
Cc: Baruch Siach <baruch@tkos.co.il>,
	Vivien Didelot <vivien.didelot@gmail.com>,
	netdev@vger.kernel.org,
	Denis Odintsov <d.odintsov@traviangames.com>,
	Hubert Feurstein <h.feurstein@gmail.com>
Subject: Re: [BUG] mv88e6xxx: tx regression in v5.3
Date: Thu, 12 Dec 2019 21:49:16 +0100	[thread overview]
Message-ID: <20191212204916.GG30053@lunn.ch> (raw)
In-Reply-To: <20191212204141.16a406cd@nic.cz>

> Baruch, if the cpu port is in 2500 base-x, remove the fixed-link and do
> this:
> 
> port@5 {
> 	reg = <5>;
> 	label = "cpu";
> 	ethernet = <&cp1_eth2>;
> 	phy-mode = "2500base-x";
> 	managed = "in-band-status";
> };
> 
> Andrew, if the dsa driver is expected to do that, the code certainly
> does not do so. For example in mv88e6xxx_port_set_cmode you have:
>  /* Default to a slow mode, so freeing up SERDES interfaces for
>   * other ports which might use them for SFPs.
>   */
>  if (mode == PHY_INTERFACE_MODE_NA)
>          mode = PHY_INTERFACE_MODE_1000BASEX;

Yah, Ports 9 and 10 of 6390X are a bit odd. They can do 10Gbps. But
only if you set the correct phy-mode. Then they will default to 10G.
If these ports are not doing 10Gbps they can lend there SERDES
interfaces to other ports. There are a few boards which want this
lending, connecting lots of SFPs using these SERDES interfaces. And
there are other boards which do use the ports at 10G as DSA links. DSA
links also default to the maximum speed of the port, and that does
work if you set the correct phy-mode.

So in general, if the port supports > 1Gbps, you need to set the
phy-mode for CPU and DSA ports. It will then default to the maximum
speed for that mode.

     Andrew

  reply	other threads:[~2019-12-12 20:49 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-11  9:48 [BUG] mv88e6xxx: tx regression in v5.3 Baruch Siach
2019-12-11 13:11 ` Andrew Lunn
2019-12-11 17:07   ` Baruch Siach
2019-12-11 17:49     ` Andrew Lunn
2019-12-12  8:50       ` Baruch Siach
2019-12-12 13:14         ` Andrew Lunn
2019-12-12 14:19           ` Andreas Tobler
2019-12-12 15:08           ` Baruch Siach
2019-12-12 15:13             ` Andrew Lunn
2019-12-12 15:23               ` Baruch Siach
2019-12-12 18:17                 ` Baruch Siach
2019-12-12 18:32                   ` Marek Behun
2019-12-12 18:48                     ` Baruch Siach
2019-12-12 18:36                 ` Marek Behun
2019-12-12 19:06                   ` Baruch Siach
2019-12-12 19:31                     ` Andrew Lunn
2019-12-12 19:41                       ` Marek Behun
2019-12-12 20:49                         ` Andrew Lunn [this message]
2019-12-15 10:13                         ` Baruch Siach
2019-12-15 11:10                           ` Baruch Siach
2019-12-15 14:53                             ` Andrew Lunn
2019-12-15 15:08                               ` Baruch Siach
2019-12-15 16:14                                 ` Andrew Lunn
2019-12-17 18:26                                   ` Baruch Siach
2019-12-18 14:30                           ` Marek Behún
2019-12-18 16:04                             ` Baruch Siach
2019-12-19  9:04                             ` Baruch Siach

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