[PATCH net-next 0/4] MSCC PHY: RGMII delays and VSC8502 support

[PATCH net-next 0/4] MSCC PHY: RGMII delays and VSC8502 support

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This series makes RGMII delays configurable as they should be on
Vitesse/Microsemi/Microchip RGMII PHYs, and adds support for a new RGMII
PHY.

Vladimir Oltean (4):
  net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay
  net: phy: mscc: accept all RGMII species in vsc85xx_mac_if_set
  net: phy: mscc: configure both RX and TX internal delays for RGMII
  net: phy: mscc: add support for VSC8502

 drivers/net/phy/mscc/mscc.h      | 21 +++++++++-------
 drivers/net/phy/mscc/mscc_main.c | 43 +++++++++++++++++++++++++++++---
 2 files changed, 52 insertions(+), 12 deletions(-)

-- 
2.17.1

[PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

There is nothing RX-specific about these clock skew values. So remove
"RX" from the name in preparation for the next patch where TX delays are
also going to be configured.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/phy/mscc/mscc.h      | 18 +++++++++---------
 drivers/net/phy/mscc/mscc_main.c |  2 +-
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
index 29ccb2c9c095..56feb14838f3 100644
--- a/drivers/net/phy/mscc/mscc.h
+++ b/drivers/net/phy/mscc/mscc.h
@@ -12,15 +12,15 @@
 #include "mscc_macsec.h"
 #endif
 
-enum rgmii_rx_clock_delay {
-	RGMII_RX_CLK_DELAY_0_2_NS = 0,
-	RGMII_RX_CLK_DELAY_0_8_NS = 1,
-	RGMII_RX_CLK_DELAY_1_1_NS = 2,
-	RGMII_RX_CLK_DELAY_1_7_NS = 3,
-	RGMII_RX_CLK_DELAY_2_0_NS = 4,
-	RGMII_RX_CLK_DELAY_2_3_NS = 5,
-	RGMII_RX_CLK_DELAY_2_6_NS = 6,
-	RGMII_RX_CLK_DELAY_3_4_NS = 7
+enum rgmii_clock_delay {
+	RGMII_CLK_DELAY_0_2_NS = 0,
+	RGMII_CLK_DELAY_0_8_NS = 1,
+	RGMII_CLK_DELAY_1_1_NS = 2,
+	RGMII_CLK_DELAY_1_7_NS = 3,
+	RGMII_CLK_DELAY_2_0_NS = 4,
+	RGMII_CLK_DELAY_2_3_NS = 5,
+	RGMII_CLK_DELAY_2_6_NS = 6,
+	RGMII_CLK_DELAY_3_4_NS = 7
 };
 
 /* Microsemi VSC85xx PHY registers */
diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c
index 2f6229a70ec1..d221583ed97a 100644
--- a/drivers/net/phy/mscc/mscc_main.c
+++ b/drivers/net/phy/mscc/mscc_main.c
@@ -525,7 +525,7 @@ static int vsc85xx_default_config(struct phy_device *phydev)
 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 	mutex_lock(&phydev->lock);
 
-	reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
+	reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
 
 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
 			      MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,
-- 
2.17.1

Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

[Andrew Lunn]

On Thu, Mar 19, 2020 at 11:16:46PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> There is nothing RX-specific about these clock skew values. So remove
> "RX" from the name in preparation for the next patch where TX delays are
> also going to be configured.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
>  drivers/net/phy/mscc/mscc.h      | 18 +++++++++---------
>  drivers/net/phy/mscc/mscc_main.c |  2 +-
>  2 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
> index 29ccb2c9c095..56feb14838f3 100644
> --- a/drivers/net/phy/mscc/mscc.h
> +++ b/drivers/net/phy/mscc/mscc.h
> @@ -12,15 +12,15 @@
>  #include "mscc_macsec.h"
>  #endif
>  
> -enum rgmii_rx_clock_delay {
> -	RGMII_RX_CLK_DELAY_0_2_NS = 0,
> -	RGMII_RX_CLK_DELAY_0_8_NS = 1,
> -	RGMII_RX_CLK_DELAY_1_1_NS = 2,
> -	RGMII_RX_CLK_DELAY_1_7_NS = 3,
> -	RGMII_RX_CLK_DELAY_2_0_NS = 4,
> -	RGMII_RX_CLK_DELAY_2_3_NS = 5,
> -	RGMII_RX_CLK_DELAY_2_6_NS = 6,
> -	RGMII_RX_CLK_DELAY_3_4_NS = 7
> +enum rgmii_clock_delay {
> +	RGMII_CLK_DELAY_0_2_NS = 0,
> +	RGMII_CLK_DELAY_0_8_NS = 1,
> +	RGMII_CLK_DELAY_1_1_NS = 2,
> +	RGMII_CLK_DELAY_1_7_NS = 3,
> +	RGMII_CLK_DELAY_2_0_NS = 4,
> +	RGMII_CLK_DELAY_2_3_NS = 5,
> +	RGMII_CLK_DELAY_2_6_NS = 6,
> +	RGMII_CLK_DELAY_3_4_NS = 7
>  };

Can this be shared?

https://www.spinics.net/lists/netdev/msg638747.html

Looks to be the same values?

Can some of the implementation be consolidated?

    Andrew

Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

[Vladimir Oltean]

Hi Andrew,

On Fri, 20 Mar 2020 at 12:09, Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Thu, Mar 19, 2020 at 11:16:46PM +0200, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > There is nothing RX-specific about these clock skew values. So remove
> > "RX" from the name in preparation for the next patch where TX delays are
> > also going to be configured.
> >
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > ---
> >  drivers/net/phy/mscc/mscc.h      | 18 +++++++++---------
> >  drivers/net/phy/mscc/mscc_main.c |  2 +-
> >  2 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
> > index 29ccb2c9c095..56feb14838f3 100644
> > --- a/drivers/net/phy/mscc/mscc.h
> > +++ b/drivers/net/phy/mscc/mscc.h
> > @@ -12,15 +12,15 @@
> >  #include "mscc_macsec.h"
> >  #endif
> >
> > -enum rgmii_rx_clock_delay {
> > -     RGMII_RX_CLK_DELAY_0_2_NS = 0,
> > -     RGMII_RX_CLK_DELAY_0_8_NS = 1,
> > -     RGMII_RX_CLK_DELAY_1_1_NS = 2,
> > -     RGMII_RX_CLK_DELAY_1_7_NS = 3,
> > -     RGMII_RX_CLK_DELAY_2_0_NS = 4,
> > -     RGMII_RX_CLK_DELAY_2_3_NS = 5,
> > -     RGMII_RX_CLK_DELAY_2_6_NS = 6,
> > -     RGMII_RX_CLK_DELAY_3_4_NS = 7
> > +enum rgmii_clock_delay {
> > +     RGMII_CLK_DELAY_0_2_NS = 0,
> > +     RGMII_CLK_DELAY_0_8_NS = 1,
> > +     RGMII_CLK_DELAY_1_1_NS = 2,
> > +     RGMII_CLK_DELAY_1_7_NS = 3,
> > +     RGMII_CLK_DELAY_2_0_NS = 4,
> > +     RGMII_CLK_DELAY_2_3_NS = 5,
> > +     RGMII_CLK_DELAY_2_6_NS = 6,
> > +     RGMII_CLK_DELAY_3_4_NS = 7
> >  };
>
> Can this be shared?
>
> https://www.spinics.net/lists/netdev/msg638747.html
>
> Looks to be the same values?
>
> Can some of the implementation be consolidated?
>
>     Andrew

2 issues:
- I don't quite understand that patch. I searched for VSC8584
documentation but I don't find any RGMII PHY? Just a SGMII/QSGMII one.
- That patch is writing to MSCC_PHY_RGMII_SETTINGS (defined to 18).
This one is writing to MSCC_PHY_RGMII_CNTL (defined to 20). And since
I have no documentation to understand why, I'm back to square 1.

Thanks,
-Vladimir

Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

[Antoine Tenart]

Hello,

Quoting Vladimir Oltean (2020-03-20 11:38:05)
> On Fri, 20 Mar 2020 at 12:09, Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > On Thu, Mar 19, 2020 at 11:16:46PM +0200, Vladimir Oltean wrote:
> > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > >
> > > There is nothing RX-specific about these clock skew values. So remove
> > > "RX" from the name in preparation for the next patch where TX delays are
> > > also going to be configured.
> > >
> > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > > ---
> > >  drivers/net/phy/mscc/mscc.h      | 18 +++++++++---------
> > >  drivers/net/phy/mscc/mscc_main.c |  2 +-
> > >  2 files changed, 10 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
> > > index 29ccb2c9c095..56feb14838f3 100644
> > > --- a/drivers/net/phy/mscc/mscc.h
> > > +++ b/drivers/net/phy/mscc/mscc.h
> > > @@ -12,15 +12,15 @@
> > >  #include "mscc_macsec.h"
> > >  #endif
> > >
> > > -enum rgmii_rx_clock_delay {
> > > -     RGMII_RX_CLK_DELAY_0_2_NS = 0,
> > > -     RGMII_RX_CLK_DELAY_0_8_NS = 1,
> > > -     RGMII_RX_CLK_DELAY_1_1_NS = 2,
> > > -     RGMII_RX_CLK_DELAY_1_7_NS = 3,
> > > -     RGMII_RX_CLK_DELAY_2_0_NS = 4,
> > > -     RGMII_RX_CLK_DELAY_2_3_NS = 5,
> > > -     RGMII_RX_CLK_DELAY_2_6_NS = 6,
> > > -     RGMII_RX_CLK_DELAY_3_4_NS = 7
> > > +enum rgmii_clock_delay {
> > > +     RGMII_CLK_DELAY_0_2_NS = 0,
> > > +     RGMII_CLK_DELAY_0_8_NS = 1,
> > > +     RGMII_CLK_DELAY_1_1_NS = 2,
> > > +     RGMII_CLK_DELAY_1_7_NS = 3,
> > > +     RGMII_CLK_DELAY_2_0_NS = 4,
> > > +     RGMII_CLK_DELAY_2_3_NS = 5,
> > > +     RGMII_CLK_DELAY_2_6_NS = 6,
> > > +     RGMII_CLK_DELAY_3_4_NS = 7
> > >  };
> >
> > Can this be shared?
> >
> > https://www.spinics.net/lists/netdev/msg638747.html
> >
> > Looks to be the same values?
> >
> > Can some of the implementation be consolidated?

> - That patch is writing to MSCC_PHY_RGMII_SETTINGS (defined to 18).
> This one is writing to MSCC_PHY_RGMII_CNTL (defined to 20). And since
> I have no documentation to understand why, I'm back to square 1.

These are two different registers, using similar values. I guess the
register was moved around as those PHYs are from the same family; but
I'm not sure if it's correct to consolidate it as we do not know for
sure. (Practically speaking the same values are used, so why not).

Thanks,
Antoine

-- 
Antoine Ténart, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

[Vladimir Oltean]

On Fri, 20 Mar 2020 at 13:05, Antoine Tenart <antoine.tenart@bootlin.com> wrote:
>
> Hello,
>
> Quoting Vladimir Oltean (2020-03-20 11:38:05)
> > On Fri, 20 Mar 2020 at 12:09, Andrew Lunn <andrew@lunn.ch> wrote:
> > >
> > > On Thu, Mar 19, 2020 at 11:16:46PM +0200, Vladimir Oltean wrote:
> > > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > > >
> > > > There is nothing RX-specific about these clock skew values. So remove
> > > > "RX" from the name in preparation for the next patch where TX delays are
> > > > also going to be configured.
> > > >
> > > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > > > ---
> > > >  drivers/net/phy/mscc/mscc.h      | 18 +++++++++---------
> > > >  drivers/net/phy/mscc/mscc_main.c |  2 +-
> > > >  2 files changed, 10 insertions(+), 10 deletions(-)
> > > >
> > > > diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
> > > > index 29ccb2c9c095..56feb14838f3 100644
> > > > --- a/drivers/net/phy/mscc/mscc.h
> > > > +++ b/drivers/net/phy/mscc/mscc.h
> > > > @@ -12,15 +12,15 @@
> > > >  #include "mscc_macsec.h"
> > > >  #endif
> > > >
> > > > -enum rgmii_rx_clock_delay {
> > > > -     RGMII_RX_CLK_DELAY_0_2_NS = 0,
> > > > -     RGMII_RX_CLK_DELAY_0_8_NS = 1,
> > > > -     RGMII_RX_CLK_DELAY_1_1_NS = 2,
> > > > -     RGMII_RX_CLK_DELAY_1_7_NS = 3,
> > > > -     RGMII_RX_CLK_DELAY_2_0_NS = 4,
> > > > -     RGMII_RX_CLK_DELAY_2_3_NS = 5,
> > > > -     RGMII_RX_CLK_DELAY_2_6_NS = 6,
> > > > -     RGMII_RX_CLK_DELAY_3_4_NS = 7
> > > > +enum rgmii_clock_delay {
> > > > +     RGMII_CLK_DELAY_0_2_NS = 0,
> > > > +     RGMII_CLK_DELAY_0_8_NS = 1,
> > > > +     RGMII_CLK_DELAY_1_1_NS = 2,
> > > > +     RGMII_CLK_DELAY_1_7_NS = 3,
> > > > +     RGMII_CLK_DELAY_2_0_NS = 4,
> > > > +     RGMII_CLK_DELAY_2_3_NS = 5,
> > > > +     RGMII_CLK_DELAY_2_6_NS = 6,
> > > > +     RGMII_CLK_DELAY_3_4_NS = 7
> > > >  };
> > >
> > > Can this be shared?
> > >
> > > https://www.spinics.net/lists/netdev/msg638747.html
> > >
> > > Looks to be the same values?
> > >
> > > Can some of the implementation be consolidated?
>
> > - That patch is writing to MSCC_PHY_RGMII_SETTINGS (defined to 18).
> > This one is writing to MSCC_PHY_RGMII_CNTL (defined to 20). And since
> > I have no documentation to understand why, I'm back to square 1.
>
> These are two different registers, using similar values. I guess the
> register was moved around as those PHYs are from the same family; but
> I'm not sure if it's correct to consolidate it as we do not know for
> sure. (Practically speaking the same values are used, so why not).
>
> Thanks,
> Antoine
>
> --
> Antoine Ténart, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

And to add to that: without documentation, I don't really know what
I'm consolidating.

 -Vladimir

Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

[Andrew Lunn]

> And to add to that: without documentation, I don't really know what
> I'm consolidating.

It looked like the defines for the delays could be shared. But if you
are not happy with this, lets leave it as is.

    Andrew

Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

[Vladimir Oltean]

On Sat, 21 Mar 2020 at 19:01, Andrew Lunn <andrew@lunn.ch> wrote:
>
> > And to add to that: without documentation, I don't really know what
> > I'm consolidating.
>
> It looked like the defines for the delays could be shared. But if you
> are not happy with this, lets leave it as is.
>
>     Andrew

To be honest, the reason why I'm not happy respinning is that I'll
need to backport these patches to a 5.4 kernel. I have nothing against
sending some further consolidation patches with Antoine's work, but
respinning this series would mean that I'd also need to backport
Antoine's patches.

Thanks,
-Vladimir

Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

[Florian Fainelli]

On 3/19/2020 2:16 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> There is nothing RX-specific about these clock skew values. So remove
> "RX" from the name in preparation for the next patch where TX delays are
> also going to be configured.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

[PATCH net-next 2/4] net: phy: mscc: accept all RGMII species in vsc85xx_mac_if_set

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

The helper for configuring the pinout of the MII side of the PHY should
do so irrespective of whether RGMII delays are used or not. So accept
the ID, TXID and RXID variants as well, not just the no-delay RGMII
variant.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/phy/mscc/mscc_main.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c
index d221583ed97a..67d96a3e0fad 100644
--- a/drivers/net/phy/mscc/mscc_main.c
+++ b/drivers/net/phy/mscc/mscc_main.c
@@ -491,6 +491,9 @@ static int vsc85xx_mac_if_set(struct phy_device *phydev,
 	reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
 	reg_val &= ~(MAC_IF_SELECTION_MASK);
 	switch (interface) {
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RGMII:
 		reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
 		break;
-- 
2.17.1

Re: [PATCH net-next 2/4] net: phy: mscc: accept all RGMII species in vsc85xx_mac_if_set

[Florian Fainelli]

On 3/19/2020 2:16 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> The helper for configuring the pinout of the MII side of the PHY should
> do so irrespective of whether RGMII delays are used or not. So accept
> the ID, TXID and RXID variants as well, not just the no-delay RGMII
> variant.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

[PATCH net-next 3/4] net: phy: mscc: configure both RX and TX internal delays for RGMII

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

The driver appears to be secretly enabling the RX clock skew
irrespective of PHY interface type, which is generally considered a big
no-no.

Make them configurable instead, and add TX internal delays when
necessary too.

While at it, configure a more canonical clock skew of 2.0 nanoseconds
than the current default of 1.1 ns.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/phy/mscc/mscc.h      |  2 ++
 drivers/net/phy/mscc/mscc_main.c | 16 +++++++++++++---
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
index 56feb14838f3..d4349a327329 100644
--- a/drivers/net/phy/mscc/mscc.h
+++ b/drivers/net/phy/mscc/mscc.h
@@ -164,6 +164,8 @@ enum rgmii_clock_delay {
 #define MSCC_PHY_RGMII_CNTL		  20
 #define RGMII_RX_CLK_DELAY_MASK		  0x0070
 #define RGMII_RX_CLK_DELAY_POS		  4
+#define RGMII_TX_CLK_DELAY_MASK		  0x0007
+#define RGMII_TX_CLK_DELAY_POS		  0
 
 #define MSCC_PHY_WOL_LOWER_MAC_ADDR	  21
 #define MSCC_PHY_WOL_MID_MAC_ADDR	  22
diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c
index 67d96a3e0fad..dd99e0cb9588 100644
--- a/drivers/net/phy/mscc/mscc_main.c
+++ b/drivers/net/phy/mscc/mscc_main.c
@@ -522,16 +522,26 @@ static int vsc85xx_mac_if_set(struct phy_device *phydev,
 
 static int vsc85xx_default_config(struct phy_device *phydev)
 {
+	u16 reg_val = 0;
 	int rc;
-	u16 reg_val;
 
 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+
+	if (!phy_interface_mode_is_rgmii(phydev->interface))
+		return 0;
+
 	mutex_lock(&phydev->lock);
 
-	reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_RX_CLK_DELAY_POS;
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_TX_CLK_DELAY_POS;
 
 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
-			      MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,
+			      MSCC_PHY_RGMII_CNTL,
+			      RGMII_RX_CLK_DELAY_MASK | RGMII_TX_CLK_DELAY_MASK,
 			      reg_val);
 
 	mutex_unlock(&phydev->lock);
-- 
2.17.1

[PATCH net-next 4/4] net: phy: mscc: add support for VSC8502

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This is a dual copper PHY with support for MII/GMII/RGMII on MAC side,
as well as a bunch of other features such as SyncE and Ring Resiliency.

I haven't tested interrupts and WoL, but I am confident that they work
since support is already present in the driver and the register map is
no different for this PHY.

PHY statistics work, PHY tunables appear to work, suspend/resume works.

Signed-off-by: Wes Li <wes.li@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/phy/mscc/mscc.h      |  1 +
 drivers/net/phy/mscc/mscc_main.c | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
index d4349a327329..ba3c1e76eac8 100644
--- a/drivers/net/phy/mscc/mscc.h
+++ b/drivers/net/phy/mscc/mscc.h
@@ -261,6 +261,7 @@ enum rgmii_clock_delay {
 /* Microsemi PHY ID's
  *   Code assumes lowest nibble is 0
  */
+#define PHY_ID_VSC8502			  0x00070630
 #define PHY_ID_VSC8504			  0x000704c0
 #define PHY_ID_VSC8514			  0x00070670
 #define PHY_ID_VSC8530			  0x00070560
diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c
index dd99e0cb9588..055df2744d7c 100644
--- a/drivers/net/phy/mscc/mscc_main.c
+++ b/drivers/net/phy/mscc/mscc_main.c
@@ -2050,6 +2050,30 @@ static int vsc85xx_probe(struct phy_device *phydev)
 
 /* Microsemi VSC85xx PHYs */
 static struct phy_driver vsc85xx_driver[] = {
+{
+	.phy_id		= PHY_ID_VSC8502,
+	.name		= "Microsemi GE VSC8502 SyncE",
+	.phy_id_mask	= 0xfffffff0,
+	/* PHY_BASIC_FEATURES */
+	.soft_reset	= &genphy_soft_reset,
+	.config_init	= &vsc85xx_config_init,
+	.config_aneg    = &vsc85xx_config_aneg,
+	.read_status	= &vsc85xx_read_status,
+	.ack_interrupt	= &vsc85xx_ack_interrupt,
+	.config_intr	= &vsc85xx_config_intr,
+	.suspend	= &genphy_suspend,
+	.resume		= &genphy_resume,
+	.probe		= &vsc85xx_probe,
+	.set_wol	= &vsc85xx_wol_set,
+	.get_wol	= &vsc85xx_wol_get,
+	.get_tunable	= &vsc85xx_get_tunable,
+	.set_tunable	= &vsc85xx_set_tunable,
+	.read_page	= &vsc85xx_phy_read_page,
+	.write_page	= &vsc85xx_phy_write_page,
+	.get_sset_count = &vsc85xx_get_sset_count,
+	.get_strings    = &vsc85xx_get_strings,
+	.get_stats      = &vsc85xx_get_stats,
+},
 {
 	.phy_id		= PHY_ID_VSC8504,
 	.name		= "Microsemi GE VSC8504 SyncE",
-- 
2.17.1

Re: [PATCH net-next 0/4] MSCC PHY: RGMII delays and VSC8502 support

[David Miller]

From: Vladimir Oltean <olteanv@gmail.com>
Date: Thu, 19 Mar 2020 23:16:45 +0200

> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> This series makes RGMII delays configurable as they should be on
> Vitesse/Microsemi/Microchip RGMII PHYs, and adds support for a new RGMII
> PHY.

Series applied, thanks Vladimir.