From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A47CC38A24 for ; Thu, 7 May 2020 08:29:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF1CB208CA for ; Thu, 7 May 2020 08:29:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588840186; bh=hK4s7mEp4L2i0jjI+ufAP/Prw7BRv28xeZTRcDf03Eg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=KdT65Z8hmqrcDyNjZXPDhxiNqdm0KsgbxaIYrqH+3WnIeCF2mHeQ7omRWTIRLGczr 0kKlxCzq9mC2nNmxiBahig/5ixk3hbfi1TNwTMyxFZ8SrB/ncmnnpUBupdsYN+WA86 polyrgJkemwGUX7u1kfG/KH27dx24syMASdw2Vg8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726408AbgEGI3n (ORCPT ); Thu, 7 May 2020 04:29:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:42314 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbgEGI3n (ORCPT ); Thu, 7 May 2020 04:29:43 -0400 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C36B12073A; Thu, 7 May 2020 08:29:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588840182; bh=hK4s7mEp4L2i0jjI+ufAP/Prw7BRv28xeZTRcDf03Eg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=xzoti7dxVqALMsVIV2N4lTmSzLlIUeq/4U2hHwg93tjPc7sx3TcKSjiPPdwPjXq2I 3NnhnGou2CFRLCWozH1qgD/HTlfDuw8TMVQk6lSkQ65uamVTMRemsxhsz62eOzJIuZ qZrkOjIc9kn/OiEE5EGDRZRlbeMTF9nzl6XUT5Ww= Date: Thu, 7 May 2020 09:29:35 +0100 From: Will Deacon To: Luke Nelson Cc: bpf@vger.kernel.org, Luke Nelson , Xi Wang , Catalin Marinas , Daniel Borkmann , Alexei Starovoitov , Zi Shen Lim , Martin KaFai Lau , Song Liu , Yonghong Song , Andrii Nakryiko , John Fastabend , KP Singh , Mark Rutland , Greg Kroah-Hartman , Thomas Gleixner , Christoffer Dall , Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, clang-built-linux@googlegroups.com Subject: Re: [RFC PATCH bpf-next 1/3] arm64: insn: Fix two bugs in encoding 32-bit logical immediates Message-ID: <20200507082934.GA28215@willie-the-truck> References: <20200507010504.26352-1-luke.r.nels@gmail.com> <20200507010504.26352-2-luke.r.nels@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200507010504.26352-2-luke.r.nels@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Luke, Thanks for the patches. On Wed, May 06, 2020 at 06:05:01PM -0700, Luke Nelson wrote: > This patch fixes two issues present in the current function for encoding > arm64 logical immediates when using the 32-bit variants of instructions. > > First, the code does not correctly reject an all-ones 32-bit immediate > and returns an undefined instruction encoding, which can crash the kernel. > The fix is to add a check for this case. > > Second, the code incorrectly rejects some 32-bit immediates that are > actually encodable as logical immediates. The root cause is that the code > uses a default mask of 64-bit all-ones, even for 32-bit immediates. This > causes an issue later on when the mask is used to fill the top bits of > the immediate with ones, shown here: > > /* > * Pattern: 0..01..10..01..1 > * > * Fill the unused top bits with ones, and check if > * the result is a valid immediate (all ones with a > * contiguous ranges of zeroes). > */ > imm |= ~mask; > if (!range_of_ones(~imm)) > return AARCH64_BREAK_FAULT; > > To see the problem, consider an immediate of the form 0..01..10..01..1, > where the upper 32 bits are zero, such as 0x80000001. The code checks > if ~(imm | ~mask) contains a range of ones: the incorrect mask yields > 1..10..01..10..0, which fails the check; the correct mask yields > 0..01..10..0, which succeeds. > > The fix is to use a 32-bit all-ones default mask for 32-bit immediates. > > Currently, the only user of this function is in > arch/arm64/kvm/va_layout.c, which uses 64-bit immediates and won't > trigger these bugs. Ah, so this isn't a fix or a bpf patch ;) I can queue it via arm64 for 5.8, along with the bpf patches since there are some other small changes pending in the arm64 bpf backend for BTI. > We tested the new code against llvm-mc with all 1,302 encodable 32-bit > logical immediates and all 5,334 encodable 64-bit logical immediates. > > Fixes: ef3935eeebff ("arm64: insn: Add encoder for bitwise operations using literals") > Co-developed-by: Xi Wang > Signed-off-by: Xi Wang > Signed-off-by: Luke Nelson > --- > arch/arm64/kernel/insn.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c > index 4a9e773a177f..42fad79546bb 100644 > --- a/arch/arm64/kernel/insn.c > +++ b/arch/arm64/kernel/insn.c > @@ -1535,7 +1535,7 @@ static u32 aarch64_encode_immediate(u64 imm, > u32 insn) > { > unsigned int immr, imms, n, ones, ror, esz, tmp; > - u64 mask = ~0UL; > + u64 mask; > > /* Can't encode full zeroes or full ones */ > if (!imm || !~imm) It's a bit grotty spreading the checks out now. How about we tweak things slightly along the lines of: diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 4a9e773a177f..60ec788eaf33 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -1535,16 +1535,10 @@ static u32 aarch64_encode_immediate(u64 imm, u32 insn) { unsigned int immr, imms, n, ones, ror, esz, tmp; - u64 mask = ~0UL; - - /* Can't encode full zeroes or full ones */ - if (!imm || !~imm) - return AARCH64_BREAK_FAULT; + u64 mask; switch (variant) { case AARCH64_INSN_VARIANT_32BIT: - if (upper_32_bits(imm)) - return AARCH64_BREAK_FAULT; esz = 32; break; case AARCH64_INSN_VARIANT_64BIT: @@ -1556,6 +1550,12 @@ static u32 aarch64_encode_immediate(u64 imm, return AARCH64_BREAK_FAULT; } + mask = GENMASK(esz - 1, 0); + + /* Can't encode full zeroes or full ones */ + if (imm & ~mask || !imm || imm == mask) + return AARCH64_BREAK_FAULT; + /* * Inverse of Replicate(). Try to spot a repeating pattern * with a pow2 stride. What do you think? Will