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From: Alex Elder <elder@linaro.org>
To: davem@davemloft.net, kuba@kernel.org
Cc: evgreen@chromium.org, subashab@codeaurora.org,
	cpratapa@codeaurora.org, bjorn.andersson@linaro.org,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH net-next 2/5] net: ipa: metadata_mask register is RX only
Date: Mon, 29 Jun 2020 16:49:16 -0500	[thread overview]
Message-ID: <20200629214919.1196017-3-elder@linaro.org> (raw)
In-Reply-To: <20200629214919.1196017-1-elder@linaro.org>

The INIT_HDR_METADATA_MASK endpoint configuration register is only
valid for RX endpoints.  Rather than writing a zero to that register
for TX endpoints, avoid writing the register at all.

Signed-off-by: Alex Elder <elder@linaro.org>
---
 drivers/net/ipa/ipa_endpoint.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c
index 3f5a41fc1997..0c2bec166066 100644
--- a/drivers/net/ipa/ipa_endpoint.c
+++ b/drivers/net/ipa/ipa_endpoint.c
@@ -527,10 +527,12 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
 	u32 val = 0;
 	u32 offset;
 
+	/* assert(!endpoint->toward_ipa); */
+
 	offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id);
 
 	/* Note that HDR_ENDIANNESS indicates big endian header fields */
-	if (!endpoint->toward_ipa && endpoint->data->qmap)
+	if (endpoint->data->qmap)
 		val = cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK);
 
 	iowrite32(val, endpoint->ipa->reg_virt + offset);
@@ -1306,10 +1308,10 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
 			(void)ipa_endpoint_program_suspend(endpoint, false);
 		ipa_endpoint_init_hdr_ext(endpoint);
 		ipa_endpoint_init_aggr(endpoint);
+		ipa_endpoint_init_hdr_metadata_mask(endpoint);
 	}
 	ipa_endpoint_init_cfg(endpoint);
 	ipa_endpoint_init_hdr(endpoint);
-	ipa_endpoint_init_hdr_metadata_mask(endpoint);
 	ipa_endpoint_init_mode(endpoint);
 	ipa_endpoint_status(endpoint);
 }
-- 
2.25.1


  parent reply	other threads:[~2020-06-29 21:50 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29 21:49 [PATCH net-next 0/5] net: ipa: endpoint configuration updates Alex Elder
2020-06-29 21:49 ` [PATCH net-next 1/5] net: ipa: head-of-line block registers are RX only Alex Elder
2020-06-30  0:35   ` Jakub Kicinski
2020-06-30  1:01     ` Alex Elder
2020-06-30  1:03       ` David Miller
2020-06-30  1:09         ` Alex Elder
2020-06-30 19:21           ` David Miller
2020-06-30 22:41             ` Alex Elder
2020-06-30 22:49               ` David Miller
2020-06-29 21:49 ` Alex Elder [this message]
2020-06-29 21:49 ` [PATCH net-next 3/5] net: ipa: mode register is TX only Alex Elder
2020-06-29 21:49 ` [PATCH net-next 4/5] net: ipa: clarify endpoint register macro constraints Alex Elder
2020-06-29 21:49 ` [PATCH net-next 5/5] net: ipa: HOL_BLOCK_EN_FMASK is a 1-bit mask Alex Elder

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