From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EABAFC433E6 for ; Thu, 16 Jul 2020 21:21:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C14EB20787 for ; Thu, 16 Jul 2020 21:21:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="N2pH37FM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727055AbgGPVVx (ORCPT ); Thu, 16 Jul 2020 17:21:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725959AbgGPVVt (ORCPT ); Thu, 16 Jul 2020 17:21:49 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03FE5C061755 for ; Thu, 16 Jul 2020 14:21:49 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id dp18so8168917ejc.8 for ; Thu, 16 Jul 2020 14:21:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=smWFYSywWLfH8RCm5bq/xiXCaN+GOIi2aGSweUXXw0k=; b=N2pH37FMfXwYF7D3jlp558rYVdxBRnVfhlfNlk37eVyCwjlSxVtGPxSekSDoJZQday srsMkiYVg1WgryvTXRy5yj8UfKC08MoDHuhnqHYUuGY/T3o4VfBbMlpjrrlxyVL7nVwL IGC7KfCnE+zhCOaQLbWaIRrOXdns2Ceo48cpaIHu8NCRWSYWnuGPBABhsVe7OGbIrOso bjDu8nHHM2JWIrk0Q6hQkY4nvX16rW7t4N8oPTYqVXT6Iua5I/Esio6ZgVs9glDGgmMe rexEttXQRKpitHPGYlVDjAlcWhiCdnKL4xyR0SZ5Oam7fc+9e79Gq1ZK+DPaEETjnhC8 ryyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=smWFYSywWLfH8RCm5bq/xiXCaN+GOIi2aGSweUXXw0k=; b=GfWNHf+iqKAovMjq/ffvkxbhu1euIkn53ND7ctiobbcHlq42HucUg0KNwfpTBLlrzS oFJjYwIyXRN1i5r9ubELj6WfE98iitcgr/N/5Zh/HTDL46rGXJXIvaad6xgybUEzdd0N HMJMa3hIfUgtZqbSOQvCAjpHVlFBa64aW5I3WWKeM+nChSgvbXoMYCSDlymy4geOWqf1 lIK0y9z3GoJJXzWnDF/dK8mrwYNEG3YH3Cd7tcB5b0/3lpWwywjbQySqqRUo7ZG2CpYw CHQ5UtTg6EyJAsM+tZby3oyg7lqgQqAFXB42BmSjU00WLDbrFTTu929VskqpmE47wbXs oESQ== X-Gm-Message-State: AOAM5303wP+qwz2HpM/Sd5uWR3yDTwFgcQ+H9MkTNS7zNhf18rEa7v6F HyREoMQOa8De4I56d5rr9xc= X-Google-Smtp-Source: ABdhPJwKYwELRGdaJRPaCmuMUOy+0hNft+WzoCqkkhTEoxDFHalB+cVd5uxMayLp9Sdvsf95qdYGmg== X-Received: by 2002:a17:906:6d56:: with SMTP id a22mr5870287ejt.440.1594934507642; Thu, 16 Jul 2020 14:21:47 -0700 (PDT) Received: from localhost.localdomain ([188.25.219.134]) by smtp.gmail.com with ESMTPSA id bq8sm6182596ejb.103.2020.07.16.14.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 14:21:47 -0700 (PDT) From: Vladimir Oltean To: kuba@kernel.org, davem@davemloft.net, netdev@vger.kernel.org Cc: richardcochran@gmail.com, jacob.e.keller@intel.com, yangbo.lu@nxp.com, xiaoliang.yang_1@nxp.com, po.liu@nxp.com, UNGLinuxDriver@microchip.com Subject: [PATCH net-next 3/3] net: mscc: ocelot: add support for PTP waveform configuration Date: Fri, 17 Jul 2020 00:20:32 +0300 Message-Id: <20200716212032.1024188-4-olteanv@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200716212032.1024188-1-olteanv@gmail.com> References: <20200716212032.1024188-1-olteanv@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org For PPS output (perout period is 1.000000000), accept the new "phase" parameter from the periodic output request structure. For both PPS and freeform output, accept the new "on" argument for specifying the duty cycle of the generated signal. Preserve the old defaults for this "on" time: 1 us for PPS, and half the period for freeform output. Also preserve the old behavior that accepted the "phase" via the "start" argument. Signed-off-by: Vladimir Oltean --- drivers/net/ethernet/mscc/ocelot_ptp.c | 74 +++++++++++++++++--------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_ptp.c b/drivers/net/ethernet/mscc/ocelot_ptp.c index 62188772a75d..1e08fe4daaef 100644 --- a/drivers/net/ethernet/mscc/ocelot_ptp.c +++ b/drivers/net/ethernet/mscc/ocelot_ptp.c @@ -184,18 +184,20 @@ int ocelot_ptp_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on) { struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); - struct timespec64 ts_start, ts_period; + struct timespec64 ts_phase, ts_period; enum ocelot_ptp_pins ptp_pin; unsigned long flags; bool pps = false; int pin = -1; + s64 wf_high; + s64 wf_low; u32 val; - s64 ns; switch (rq->type) { case PTP_CLK_REQ_PEROUT: /* Reject requests with unsupported flags */ - if (rq->perout.flags) + if (rq->perout.flags & ~(PTP_PEROUT_DUTY_CYCLE | + PTP_PEROUT_PHASE)) return -EOPNOTSUPP; pin = ptp_find_pin(ocelot->ptp_clock, PTP_PF_PEROUT, @@ -211,22 +213,12 @@ int ocelot_ptp_enable(struct ptp_clock_info *ptp, else return -EBUSY; - ts_start.tv_sec = rq->perout.start.sec; - ts_start.tv_nsec = rq->perout.start.nsec; ts_period.tv_sec = rq->perout.period.sec; ts_period.tv_nsec = rq->perout.period.nsec; if (ts_period.tv_sec == 1 && ts_period.tv_nsec == 0) pps = true; - if (ts_start.tv_sec || (ts_start.tv_nsec && !pps)) { - dev_warn(ocelot->dev, - "Absolute start time not supported!\n"); - dev_warn(ocelot->dev, - "Accept nsec for PPS phase adjustment, otherwise start time should be 0 0.\n"); - return -EINVAL; - } - /* Handle turning off */ if (!on) { spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); @@ -236,16 +228,48 @@ int ocelot_ptp_enable(struct ptp_clock_info *ptp, break; } + if (rq->perout.flags & PTP_PEROUT_PHASE) { + ts_phase.tv_sec = rq->perout.phase.sec; + ts_phase.tv_nsec = rq->perout.phase.nsec; + } else { + /* Compatibility */ + ts_phase.tv_sec = rq->perout.start.sec; + ts_phase.tv_nsec = rq->perout.start.nsec; + } + if (ts_phase.tv_sec || (ts_phase.tv_nsec && !pps)) { + dev_warn(ocelot->dev, + "Absolute start time not supported!\n"); + dev_warn(ocelot->dev, + "Accept nsec for PPS phase adjustment, otherwise start time should be 0 0.\n"); + return -EINVAL; + } + + /* Calculate waveform high and low times */ + if (rq->perout.flags & PTP_PEROUT_DUTY_CYCLE) { + struct timespec64 ts_on; + + ts_on.tv_sec = rq->perout.on.sec; + ts_on.tv_nsec = rq->perout.on.nsec; + + wf_high = timespec64_to_ns(&ts_on); + } else { + if (pps) { + wf_high = 1000; + } else { + wf_high = timespec64_to_ns(&ts_period); + wf_high = div_s64(wf_high, 2); + } + } + + wf_low = timespec64_to_ns(&ts_period); + wf_low -= wf_high; + /* Handle PPS request */ if (pps) { spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); - /* Pulse generated perout.start.nsec after TOD has - * increased seconds. - * Pulse width is set to 1us. - */ - ocelot_write_rix(ocelot, ts_start.tv_nsec, + ocelot_write_rix(ocelot, ts_phase.tv_nsec, PTP_PIN_WF_LOW_PERIOD, ptp_pin); - ocelot_write_rix(ocelot, NSEC_PER_SEC / 2, + ocelot_write_rix(ocelot, wf_high, PTP_PIN_WF_HIGH_PERIOD, ptp_pin); val = PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_CLOCK); val |= PTP_PIN_CFG_SYNC; @@ -255,14 +279,16 @@ int ocelot_ptp_enable(struct ptp_clock_info *ptp, } /* Handle periodic clock */ - ns = timespec64_to_ns(&ts_period); - ns = ns >> 1; - if (ns > 0x3fffffff || ns <= 0x6) + if (wf_high > 0x3fffffff || wf_high <= 0x6) + return -EINVAL; + if (wf_low > 0x3fffffff || wf_low <= 0x6) return -EINVAL; spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); - ocelot_write_rix(ocelot, ns, PTP_PIN_WF_LOW_PERIOD, ptp_pin); - ocelot_write_rix(ocelot, ns, PTP_PIN_WF_HIGH_PERIOD, ptp_pin); + ocelot_write_rix(ocelot, wf_low, PTP_PIN_WF_LOW_PERIOD, + ptp_pin); + ocelot_write_rix(ocelot, wf_high, PTP_PIN_WF_HIGH_PERIOD, + ptp_pin); val = PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_CLOCK); ocelot_write_rix(ocelot, val, PTP_PIN_CFG, ptp_pin); spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); -- 2.25.1