Re: [PATCH net-next 3/3] net: dsa: mv88e6xxx: add support for 88E6393X from Amethyst family

[Russell King - ARM Linux admin <linux@armlinux.org.uk>]

On Sat, Aug 22, 2020 at 06:49:46PM +0200, Andrew Lunn wrote:
> > --- a/drivers/net/dsa/mv88e6xxx/port.c
> > +++ b/drivers/net/dsa/mv88e6xxx/port.c
> > @@ -187,11 +187,16 @@ static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip,
> >  		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
> >  		break;
> >  	case 2500:
> > -		if (alt_bit)
> > -			ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
> > -				MV88E6390_PORT_MAC_CTL_ALTSPEED;
> > +		if (chip->info->family == MV88E6XXX_FAMILY_6393)
> > +			ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
> >  		else
> >  			ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
> > +		if (alt_bit)
> > +			ctrl |= MV88E6390_PORT_MAC_CTL_ALTSPEED;
> > +		break;
> > +	case 5000:
> > +		ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
> > +			MV88E6390_PORT_MAC_CTL_ALTSPEED;
> >  		break;
> >  	case 10000:
> >  		/* all bits set, fall through... */
> 
> This is getting more and more complex. Maybe it is time to refactor it?

However, please note that the speed/duplex that is passed through
phylink from phylib is the _media_ speed.  If you are using RXAUI
(for example) then the link should be running at 10G speed,
especially if the PHY is doing rate matching.  The only other thing
is if rate matching is in use but no flow control, then limiting the
egress rate is needed.

-- 
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