From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AEE7C43461 for ; Thu, 3 Sep 2020 21:53:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0BA2820678 for ; Thu, 3 Sep 2020 21:53:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729353AbgICVxf (ORCPT ); Thu, 3 Sep 2020 17:53:35 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:41600 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726679AbgICVxf (ORCPT ); Thu, 3 Sep 2020 17:53:35 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kDxAh-00D6wK-ED; Thu, 03 Sep 2020 23:53:31 +0200 Date: Thu, 3 Sep 2020 23:53:31 +0200 From: Andrew Lunn To: Marek Vasut Cc: netdev@vger.kernel.org, Christoph Niedermaier , "David S . Miller" , NXP Linux Team , Richard Leitner , Shawn Guo Subject: Re: [PATCH] net: fec: Fix PHY init after phy_reset_after_clk_enable() Message-ID: <20200903215331.GG3112546@lunn.ch> References: <20200903202712.143878-1-marex@denx.de> <20200903210011.GD3112546@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Thu, Sep 03, 2020 at 11:36:39PM +0200, Marek Vasut wrote: > On 9/3/20 11:00 PM, Andrew Lunn wrote: > > On Thu, Sep 03, 2020 at 10:27:12PM +0200, Marek Vasut wrote: > >> The phy_reset_after_clk_enable() does a PHY reset, which means the PHY > >> loses its register settings. The fec_enet_mii_probe() starts the PHY > >> and does the necessary calls to configure the PHY via PHY framework, > >> and loads the correct register settings into the PHY. Therefore, > >> fec_enet_mii_probe() should be called only after the PHY has been > >> reset, not before as it is now. > > > > I think this patch is related to what Florian is currently doing with > > PHY clocks. > > Which is what ? Details please. Have you used b4 before? b4 am 20200903043947.3272453-1-f.fainelli@gmail.com > > I think a better fix for the original problem is for the SMSC PHY > > driver to control the clock itself. If it clk_prepare_enables() the > > clock, it knows it will not be shut off again by the FEC run time > > power management. > > The FEC MAC is responsible for generating the clock, the PHY clock are > not part of the clock framework as far as I can tell. I'm not sure this is true. At least: https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi#L123 and there are a few more examples: imx6ul-14x14-evk.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; imx6ul-kontron-n6x1x-s.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; imx6ul-kontron-n6x1x-som-common.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; imx6ull-myir-mys-6ulx.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; imx6ul-phytec-phycore-som.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; Maybe it is just IMX6? Andrew