From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC222C433E2 for ; Thu, 17 Sep 2020 13:12:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7AD092083B for ; Thu, 17 Sep 2020 13:12:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727039AbgIQNMw (ORCPT ); Thu, 17 Sep 2020 09:12:52 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:40584 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727055AbgIQNLt (ORCPT ); Thu, 17 Sep 2020 09:11:49 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kIthA-00F550-I6; Thu, 17 Sep 2020 15:11:28 +0200 Date: Thu, 17 Sep 2020 15:11:28 +0200 From: Andrew Lunn To: Florian Fainelli Cc: netdev@vger.kernel.org, opendmb@gmail.com, Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , "open list:BROADCOM ETHERNET PHY DRIVERS" , open list Subject: Re: [PATCH net-next v2] net: phy: bcm7xxx: request and manage GPHY clock Message-ID: <20200917131128.GK3526428@lunn.ch> References: <20200917020413.2313461-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200917020413.2313461-1-f.fainelli@gmail.com> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Wed, Sep 16, 2020 at 07:04:13PM -0700, Florian Fainelli wrote: > The internal Gigabit PHY on Broadcom STB chips has a digital clock which > drives its MDIO interface among other things, the driver now requests > and manage that clock during .probe() and .remove() accordingly. > > Because the PHY driver can be probed with the clocks turned off we need > to apply the dummy BMSR workaround during the driver probe function to > ensure subsequent MDIO read or write towards the PHY will succeed. Hi Florian Is it worth mentioning this in the DT binding? It is all pretty much standard lego pieces, but it has taken you a while to assemble them in the correct way. So giving hits to others who might want to uses these STB chips could be nice. Andrew