On 20-09-17 21:29:41, David Bilsby wrote:
> On 17/09/2020 07:42, Petko Manolov wrote:
> > On 20-09-16 22:32:03, David Bilsby wrote:
> > > Hi
> > > 
> > > Would you consider making the PhyLink modifications to the Altera TSE 
> > > driver public as this would be very useful for a board we have which uses 
> > > an SFP PHY connected to the TSE core via I2C. Currently we are using a 
> > > fibre SFP and fixing the speed to 1G but would really like to be able to 
> > > use a copper SFP which needs to do negotiation.
> > Well, definitely yes.
> > 
> > The driver isn't 100% finished, but it mostly works.  One significant 
> > downside is the kernel version i had to port it to: 4.19.  IIRC there is API 
> > change so my current patches can't be applied to 5.x kernels.  Also, i could 
> > not finish the upstreaming as the customer device i worked on had to be 
> > returned.
>
> Interesting about kernel versions as we have just moved to the latest 5.4.44 
> lts kernel as suggested on Rocketboard for Arria 10s. We had been having 
> issues with 4.19 kernel which seem to have been resolved in the 5.4.44.

Always use mainline (and new) kernels.  If possible... ;)

> > However, given access to Altera TSE capable device (which i don't have atm), 
> > running a recent kernel, i'll gladly finish the upstreaming.
>
> I would be happy to take what you have at the moment, pre-upstreaming, and see 
> if I can get it going on the latter kernel, and hopefully provide some testing 
> feedback. Obviously pass any changes back for you to review and include as 
> part of your original work.

There you go.


		Petko