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[85.73.10.175]) by smtp.gmail.com with ESMTPSA id n5sm5290154wrm.2.2020.10.29.07.21.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2020 07:21:03 -0700 (PDT) Date: Thu, 29 Oct 2020 16:21:00 +0200 From: Ilias Apalodimas To: Andrew Lunn Cc: Ard Biesheuvel , Daniel Thompson , Sumit Garg , Alex =?iso-8859-1?Q?Benn=E9e?= , Masami Hiramatsu , Steve McIntyre , "open list:BPF JIT for MIPS (32-BIT AND 64-BIT)" , Willy Liu , "David S. Miller" , Jakub Kicinski , Sasha Levin , Florian Fainelli , Heiner Kallweit , Masahisa Kojima Subject: Re: realtek PHY commit bbc4d71d63549 causes regression Message-ID: <20201029142100.GA70245@apalos.home> References: <20201017194904.GP456889@lunn.ch> <20201017230226.GV456889@lunn.ch> <20201018154502.GZ456889@lunn.ch> <20201025142856.GC792004@lunn.ch> <20201025144258.GE792004@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201025144258.GE792004@lunn.ch> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Andrew On Sun, Oct 25, 2020 at 03:42:58PM +0100, Andrew Lunn wrote: > On Sun, Oct 25, 2020 at 03:34:06PM +0100, Ard Biesheuvel wrote: > > On Sun, 25 Oct 2020 at 15:29, Andrew Lunn wrote: > > > > > > On Sun, Oct 25, 2020 at 03:16:36PM +0100, Ard Biesheuvel wrote: > > > > On Sun, 18 Oct 2020 at 17:45, Andrew Lunn wrote: > > > > > > > > > > > However, that leaves the question why bbc4d71d63549bcd was backported, > > > > > > although I understand why the discussion is a bit trickier there. But > > > > > > if it did not fix a regression, only broken code that never worked in > > > > > > the first place, I am not convinced it belongs in -stable. > > > > > > > > > > Please ask Serge Semin what platform he tested on. I kind of expect it > > > > > worked for him, in some limited way, enough that it passed his > > > > > testing. > > > > > > > > > > > > > I'll make a note here that a rather large number of platforms got > > > > broken by the same fix for the Realtek PHY driver: > > > > > > > > https://lore.kernel.org/lkml/?q=bbc4d71d6354 > > > > > > > > I seriously doubt whether disabling TX/RX delay when it is enabled by > > > > h/w straps is the right thing to do here. > > > > > > The device tree is explicitly asking for rgmii. If it wanted the > > > hardware left alone, it should of used PHY_INTERFACE_MODE_NA. > > > > > > > Would you suggest that these DTs remove the phy-mode instead? As I > > don't see anyone proposing that. > > What is also O.K, for most MAC drivers. Some might enforce it is > present, in which case, you can set it to "", which will get parsed as > PHY_INTERFACE_MODE_NA. But a few MAC drivers might configure there MII > bus depending on the PHY mode, RGMII vs GMII. > > Andrew What about reverting the realtek PHY commit from stable? As Ard said it doesn't really fix anything (usage wise) and causes a bunch of problems. If I understand correctly we have 3 options: 1. 'Hack' the drivers in stable to fix it (and most of those hacks will take a long time to remove) 2. Update DTE of all affected devices, backport it to stable and force users to update 3. Revert the PHY commit imho [3] is the least painful solution. Thanks /Ilias