From: Steen Hegelund <steen.hegelund@microchip.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Masahiro Yamada <masahiroy@kernel.org>,
Lars Povlsen <lars.povlsen@microchip.com>,
Bjarni Jonasson <bjarni.jonasson@microchip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Microsemi List <microsemi@lists.bootlin.com>,
<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH 2/3] net: sparx5: Add Sparx5 switchdev driver
Date: Mon, 30 Nov 2020 15:42:06 +0100 [thread overview]
Message-ID: <20201130144206.g7hnvwrtbblgblpm@mchp-dev-shegelun> (raw)
In-Reply-To: <20201129173520.GF2234159@lunn.ch>
On 29.11.2020 18:35, Andrew Lunn wrote:
>EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
>> +#define SPX5_RD_(sparx5, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth) \
>> + readl(spx5_addr((sparx5)->regs, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth))
>> +
>> +#define SPX5_INST_RD_(iomem, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth) \
>> + readl(spx5_inst_addr(iomem, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth))
>> +
>> +#define SPX5_WR_(val, sparx5, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth) \
>> + writel(val, spx5_addr((sparx5)->regs, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth))
>> +
>> +#define SPX5_INST_WR_(val, iomem, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth) \
>> + writel(val, spx5_inst_addr(iomem, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth))
>> +
>> +#define SPX5_RMW_(val, mask, sparx5, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth) \
>> + do { \
>> + u32 _v_; \
>> + u32 _m_ = mask; \
>> + void __iomem *addr = \
>> + spx5_addr((sparx5)->regs, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth); \
>> + _v_ = readl(addr); \
>> + _v_ = ((_v_ & ~(_m_)) | ((val) & (_m_))); \
>> + writel(_v_, addr); \
>> + } while (0)
>> +
>> +#define SPX5_INST_RMW_(val, mask, iomem, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth) \
>> + do { \
>> + u32 _v_; \
>> + u32 _m_ = mask; \
>> + void __iomem *addr = \
>> + spx5_inst_addr(iomem, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth); \
>> + _v_ = readl(addr); \
>> + _v_ = ((_v_ & ~(_m_)) | ((val) & (_m_))); \
>> + writel(_v_, addr); \
>> + } while (0)
>> +
>> +#define SPX5_REG_RD_(regaddr) \
>> + readl(regaddr)
>> +
>> +#define SPX5_REG_WR_(val, regaddr) \
>> + writel(val, regaddr)
>> +
>> +#define SPX5_REG_RMW_(val, mask, regaddr) \
>> + do { \
>> + u32 _v_; \
>> + u32 _m_ = mask; \
>> + void __iomem *_r_ = regaddr; \
>> + _v_ = readl(_r_); \
>> + _v_ = ((_v_ & ~(_m_)) | ((val) & (_m_))); \
>> + writel(_v_, _r_); \
>> + } while (0)
>> +
>> +#define SPX5_REG_GET_(sparx5, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth) \
>> + spx5_addr((sparx5)->regs, id, tinst, tcnt, \
>> + gbase, ginst, gcnt, gwidth, \
>> + raddr, rinst, rcnt, rwidth)
>> +
>> +#define SPX5_RD(...) SPX5_RD_(__VA_ARGS__)
>> +#define SPX5_WR(...) SPX5_WR_(__VA_ARGS__)
>> +#define SPX5_RMW(...) SPX5_RMW_(__VA_ARGS__)
>> +#define SPX5_INST_RD(...) SPX5_INST_RD_(__VA_ARGS__)
>> +#define SPX5_INST_WR(...) SPX5_INST_WR_(__VA_ARGS__)
>> +#define SPX5_INST_RMW(...) SPX5_INST_RMW_(__VA_ARGS__)
>> +#define SPX5_INST_GET(sparx5, id, tinst) ((sparx5)->regs[(id) + (tinst)])
>> +#define SPX5_REG_RMW(...) SPX5_REG_RMW_(__VA_ARGS__)
>> +#define SPX5_REG_WR(...) SPX5_REG_WR_(__VA_ARGS__)
>> +#define SPX5_REG_RD(...) SPX5_REG_RD_(__VA_ARGS__)
>> +#define SPX5_REG_GET(...) SPX5_REG_GET_(__VA_ARGS__)
>
>I don't see any reason for macro magic here. If this just left over
>from HAL code? Please turn this all into functions.
>
> Andrew
>
Thanks for the comment. I will transform this into functions.
BR
Steen
---------------------------------------
Steen Hegelund
steen.hegelund@microchip.com
next prev parent reply other threads:[~2020-11-30 14:43 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-27 13:33 [RFC PATCH 0/3] net: Adding the Sparx5 Switch Driver Steen Hegelund
2020-11-27 13:33 ` [RFC PATCH 1/3] dt-bindings: net: sparx5: Add sparx5-switch bindings Steen Hegelund
2020-11-27 17:00 ` Andrew Lunn
2020-11-30 13:09 ` Steen Hegelund
2020-11-30 14:05 ` Andrew Lunn
2020-11-30 15:33 ` Steen Hegelund
2020-11-27 13:33 ` [RFC PATCH 2/3] net: sparx5: Add Sparx5 switchdev driver Steen Hegelund
2020-11-27 17:15 ` Andrew Lunn
2020-11-30 13:13 ` Steen Hegelund
2020-12-07 13:33 ` Jiri Pirko
2020-11-28 18:45 ` Andrew Lunn
2020-11-30 13:17 ` Steen Hegelund
2020-11-28 19:03 ` Andrew Lunn
2020-11-30 13:28 ` Steen Hegelund
2020-11-30 15:34 ` Andrew Lunn
2020-11-28 19:06 ` Andrew Lunn
2020-11-28 19:37 ` Russell King - ARM Linux admin
2020-11-28 20:07 ` Alexandre Belloni
2020-11-28 20:21 ` Andrew Lunn
2020-11-28 22:28 ` Russell King - ARM Linux admin
2020-11-29 10:52 ` Russell King - ARM Linux admin
2020-11-29 11:28 ` Russell King - ARM Linux admin
2020-11-30 14:39 ` Steen Hegelund
2020-11-30 14:54 ` Russell King - ARM Linux admin
2020-11-29 11:30 ` Russell King - ARM Linux admin
2020-11-30 14:30 ` Steen Hegelund
2020-11-30 14:50 ` Russell King - ARM Linux admin
2020-11-30 14:15 ` Steen Hegelund
2020-11-30 14:52 ` Russell King - ARM Linux admin
2020-11-30 14:10 ` Steen Hegelund
2020-11-28 19:24 ` Andrew Lunn
2020-12-01 11:11 ` Lars Povlsen
2020-11-29 17:16 ` Andrew Lunn
2020-11-30 13:33 ` Steen Hegelund
2020-11-29 17:26 ` Andrew Lunn
2020-11-30 13:31 ` Steen Hegelund
2020-11-29 17:35 ` Andrew Lunn
2020-11-30 14:42 ` Steen Hegelund [this message]
2020-11-27 13:33 ` [RFC PATCH 3/3] arm64: dts: sparx5: Add the Sparx5 switch node Steen Hegelund
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