From: Peter Vollmer <peter.vollmer@gmail.com>
To: Tobias Waldekranz <tobias@waldekranz.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
Network Development <netdev@vger.kernel.org>
Subject: Re: dsa/mv88e6xxx: leaking packets on MV88E6341 switch
Date: Tue, 1 Dec 2020 09:49:17 +0100 [thread overview]
Message-ID: <20201201084916.GA6059@unassigned-hostname.unassigned-domain> (raw)
In-Reply-To: <87y2in94o7.fsf@waldekranz.com>
On Thu, Nov 26, 2020 at 10:41:44PM +0100, Tobias Waldekranz wrote:
> On Wed, Nov 25, 2020 at 15:09, Peter Vollmer <peter.vollmer@gmail.com> wrote:
> > - pinging from client0 (connected to lan0 ) to the bridge IP, the ping
> > requests (only the requests) are also seen on client1 connected to
> > lan1
>
> This is the expected behavior of the current implementation I am
> afraid. It stems from the fact that the CPU responds to the echo request
> (or to any other request for that matter) with a FROM_CPU. This means
> that no learning takes place, and the SA of br0 will thus never reach
> the switch's FDB. So while client0 knows the MAC of br0, the switch
> (very counter-intuitively) does not.
>
> The result is that the unicast echo request sent by client0 is flooded
> as unknown unicast by the switch. This way it reaches the CPU but also,
> as you have discovered, all other ports that allow unknown unicast to
> egress.
>
Thanks for this explanation. Would there be a way to inject the br0 MAC
into the switch FDB using 'bridge fdb' or some other tool as a
workaround ?
And is this behaviour the same with all other DSA capable
switches (or at least the mv88e6xxx ones)? Will this change eventually
after the implementation is complete ?
Thanks and best regards
Peter
next prev parent reply other threads:[~2020-12-01 8:50 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-30 10:09 dsa/mv88e6xxx: leaking packets on MV88E6341 switch Peter Vollmer
2020-09-30 10:28 ` Vladimir Oltean
2020-09-30 11:57 ` Peter Vollmer
2020-09-30 19:19 ` Andrew Lunn
2020-10-01 6:21 ` Peter Vollmer
2020-11-25 14:09 ` Peter Vollmer
2020-11-26 21:41 ` Tobias Waldekranz
2020-11-26 22:23 ` Andrew Lunn
2020-12-01 9:00 ` Peter Vollmer
2020-12-01 13:58 ` Andrew Lunn
2020-12-01 8:49 ` Peter Vollmer [this message]
2020-12-01 12:29 ` Tobias Waldekranz
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