From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16636C433E9 for ; Tue, 22 Dec 2020 15:09:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA41522583 for ; Tue, 22 Dec 2020 15:09:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728081AbgLVPJ3 (ORCPT ); Tue, 22 Dec 2020 10:09:29 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:37082 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726920AbgLVPJ3 (ORCPT ); Tue, 22 Dec 2020 10:09:29 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1krjHC-00DOur-V5; Tue, 22 Dec 2020 16:08:38 +0100 Date: Tue, 22 Dec 2020 16:08:38 +0100 From: Andrew Lunn To: Bjarni Jonasson Cc: Steen Hegelund , "David S. Miller" , Jakub Kicinski , Russell King , Lars Povlsen , Microchip Linux Driver Support , Alexandre Belloni , Madalin Bucur , Nicolas Ferre , Mark Einon , Masahiro Yamada , Arnd Bergmann , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH v2 4/8] net: sparx5: add port module support Message-ID: <20201222150838.GN3107610@lunn.ch> References: <20201217075134.919699-1-steen.hegelund@microchip.com> <20201217075134.919699-5-steen.hegelund@microchip.com> <20201220233543.GB3107610@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > > > +static int sparx5_port_verify_speed(struct sparx5 *sparx5, > > > + struct sparx5_port *port, > > > + struct sparx5_port_config *conf) > > > +{ > > > + case PHY_INTERFACE_MODE_SGMII: > > > + if (conf->speed != SPEED_1000 && > > > + conf->speed != SPEED_100 && > > > + conf->speed != SPEED_10 && > > > + conf->speed != SPEED_2500) > > > + return sparx5_port_error(port, conf, > > > SPX5_PERR_SPEED); > > > > Is it really SGMII over clocked at 2500? Or 2500BaseX? > > Yes the SGMII mode in the serdes driver is overclocked. > Nothing in the switch driver needs changing when changing between > speeds 1G/2G5. So it continues to use the SGMII inband signalling? There is a lot of confusion in this area, but SGMII inband signalling overclocked does not make much sense. So it is more likely to be using 2500BaseX. Andrew