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Miller" , Jakub Kicinski , , , , , , , , , , Parav Pandit , Saeed Mahameed Subject: Re: [net-next V9 14/14] net/mlx5: Add devlink subfunction port documentation Message-ID: <20210125130654.GI4147@nvidia.com> References: <20210121085237.137919-1-saeed@kernel.org> <20210121085237.137919-15-saeed@kernel.org> <20210122001157.GE4147@nvidia.com> <89d0c6de-18e3-5728-a220-3440ca263616@intel.com> Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <89d0c6de-18e3-5728-a220-3440ca263616@intel.com> X-ClientProxiedBy: BLAPR03CA0057.namprd03.prod.outlook.com (2603:10b6:208:32d::32) To DM6PR12MB3834.namprd12.prod.outlook.com (2603:10b6:5:14a::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mlx.ziepe.ca (142.162.115.133) by BLAPR03CA0057.namprd03.prod.outlook.com (2603:10b6:208:32d::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.12 via Frontend Transport; Mon, 25 Jan 2021 13:06:56 +0000 Received: from jgg by mlx with local (Exim 4.94) (envelope-from ) id 1l41a2-006UR5-HS; Mon, 25 Jan 2021 09:06:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611580025; bh=GOxnf/1FDRpkmxX0Rfc95kJhR6v5dbRL9ZP6sX1B9XI=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:Date: From:To:CC:Subject:Message-ID:References:Content-Type: Content-Disposition:Content-Transfer-Encoding:In-Reply-To: X-ClientProxiedBy:MIME-Version: X-MS-Exchange-MessageSentRepresentingType; b=No/XmjyJwcyJ16fHZy0vx3rFK7qdfjw37B853q5YkvIN2RCEuF0JxlbkC+jPxKRCv v56dqq/RxiYmOSltseP6CZYigFtruotot5HWKwY2ss4mNddKV8E85LJbkQmSgszSbb DmnbjqoOiEKohk/3o/I5MsVmAGK3K/KvB8mq1vs4pYZ7E9umUps3XoR0ZZkY8sM/xn /ABZUOXfUWSVbj/3i6Pt8XZUxLgKKoBLlBHmfhIq2tsK5QyL9psW+8/NpubRxMfYC8 sScOGkcF3fPLgJGAqcxlsl+P/64lym/TREKp8olDHxufdbNx/+7kUtOnMMB/b9Lcfd zOqNCmQif7c2A== Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Sat, Jan 23, 2021 at 12:09:15PM -0800, Samudrala, Sridhar wrote: > > The other aux devices represent the subsystem split of the mlx5 driver > > - mlx5_core creates them and each subsystem in turn binds to the > > mlx5_core driver. This already exists, and Intel will be doing this as > > well whenever the RDMA driver is posted again.. >=20 > Yes. I see that the intel RDMA patches are now submitted. We are > creating an aux device to expose RDMA functionality, but=C2=A0 not > planning to create an aux device for ethernet subsystem on a PF/SF > as the function-level pci/aux device can represent the default > ethernet. That is because the ethernet and shared code are all in the same module You may find this becomes inconvenient when you want to add something like SF, where there is alot of merit to having uniformity in the ethernet driver. Jason