From: Jason Gunthorpe <jgg@nvidia.com>
To: Edwin Peer <edwin.peer@broadcom.com>
Cc: Parav Pandit <parav@nvidia.com>,
Saeed Mahameed <saeed@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>, netdev <netdev@vger.kernel.org>,
"linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>,
Alexander Duyck <alexander.duyck@gmail.com>,
Sridhar Samudrala <sridhar.samudrala@intel.com>,
David Ahern <dsahern@kernel.org>,
Kiran Patil <kiran.patil@intel.com>,
Jacob Keller <jacob.e.keller@intel.com>,
"Ertman, David M" <david.m.ertman@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Saeed Mahameed <saeedm@nvidia.com>
Subject: Re: [pull request][net-next V10 00/14] Add mlx5 subfunction support
Date: Mon, 25 Jan 2021 15:59:05 -0400 [thread overview]
Message-ID: <20210125195905.GA4147@nvidia.com> (raw)
In-Reply-To: <CAKOOJTx7ogAvUkT5y8vKYp=KB+VSbe0MgXg5PuvjEiU_dO_5YA@mail.gmail.com>
On Mon, Jan 25, 2021 at 11:34:49AM -0800, Edwin Peer wrote:
> What do these amount to in practice? Presumably config space is backed
> by normal memory controlled by firmware. Do VF's need to expose ECAM?
> Also, don't MSI tables come out of the BAR budget? Is the required BAR
> space necessarily more than any other addressable unit that can be
> delegated to a SF?
Every writable data mandated by the PCI spec requires very expensive
on-die SRAM to store it.
We've seen Intel drivers that show their SIOV ADIs don't even have a
register file and the only PCI presence is just a write-only doorbell
page in the BAR.
It is hard to argue a write-only register in a BAR page vs all the
SRIOV trappings when it comes to HW cost.
Jason
next prev parent reply other threads:[~2021-01-25 20:02 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-22 19:36 [pull request][net-next V10 00/14] Add mlx5 subfunction support Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 01/14] devlink: Prepare code to fill multiple port function attributes Saeed Mahameed
2021-01-29 1:40 ` patchwork-bot+netdevbpf
2021-01-22 19:36 ` [net-next V10 02/14] devlink: Introduce PCI SF port flavour and port attribute Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 03/14] devlink: Support add and delete devlink port Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 04/14] devlink: Support get and set state of port function Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 05/14] net/mlx5: Introduce vhca state event notifier Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 06/14] net/mlx5: SF, Add auxiliary device support Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 07/14] net/mlx5: SF, Add auxiliary device driver Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 08/14] net/mlx5: E-switch, Prepare eswitch to handle SF vport Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 09/14] net/mlx5: E-switch, Add eswitch helpers for " Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 10/14] net/mlx5: SF, Add port add delete functionality Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 11/14] net/mlx5: SF, Port function state change support Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 12/14] devlink: Add devlink port documentation Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 13/14] devlink: Extend devlink port documentation for subfunctions Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 14/14] net/mlx5: Add devlink subfunction port documentation Saeed Mahameed
2021-01-24 20:47 ` [pull request][net-next V10 00/14] Add mlx5 subfunction support Edwin Peer
2021-01-25 10:57 ` Parav Pandit
2021-01-25 13:22 ` Jason Gunthorpe
2021-01-25 19:23 ` Edwin Peer
2021-01-25 19:49 ` Jason Gunthorpe
2021-01-25 20:05 ` Edwin Peer
2021-01-25 20:22 ` Michael Chan
2021-01-25 20:26 ` Parav Pandit
2021-01-25 18:35 ` Edwin Peer
2021-01-25 19:34 ` Edwin Peer
2021-01-25 19:59 ` Jason Gunthorpe [this message]
2021-01-25 20:22 ` Edwin Peer
2021-01-25 20:41 ` Jason Gunthorpe
2021-01-25 21:23 ` Edwin Peer
2021-01-25 23:13 ` Jason Gunthorpe
2021-01-27 1:34 ` Jakub Kicinski
2021-01-29 0:03 ` Saeed Mahameed
2021-01-29 0:11 ` Jakub Kicinski
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