From: Saeed Mahameed <saeed@kernel.org>
To: Jakub Kicinski <kuba@kernel.org>
Cc: "David S. Miller" <davem@davemloft.net>,
netdev@vger.kernel.org, linux-rdma@vger.kernel.org,
Leon Romanovsky <leonro@nvidia.com>,
Yevgeny Kliteynik <kliteyn@nvidia.com>,
Erez Shitrit <erezsh@nvidia.com>, Alex Vesker <valex@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>
Subject: [net-next 08/11] net/mlx5: DR, Use the right size when writing partial STE into HW
Date: Fri, 29 Jan 2021 18:26:15 -0800 [thread overview]
Message-ID: <20210130022618.317351-9-saeed@kernel.org> (raw)
In-Reply-To: <20210130022618.317351-1-saeed@kernel.org>
From: Yevgeny Kliteynik <kliteyn@nvidia.com>
In these cases we need to update only the ctrl area of the STE.
So it is better to write only the control 32B and avoid copying
the unneeded reduced 48B (control 32B + tag 16B).
Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
.../ethernet/mellanox/mlx5/core/steering/dr_rule.c | 12 ++++++++----
.../ethernet/mellanox/mlx5/core/steering/dr_ste.c | 2 +-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c
index ddcb7017e121..fcea2a21abe9 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c
@@ -30,7 +30,7 @@ static int dr_rule_append_to_miss_list(struct mlx5dr_ste_ctx *ste_ctx,
mlx5dr_ste_get_icm_addr(new_last_ste));
list_add_tail(&new_last_ste->miss_list_node, miss_list);
- mlx5dr_send_fill_and_append_ste_send_info(last_ste, DR_STE_SIZE_REDUCED,
+ mlx5dr_send_fill_and_append_ste_send_info(last_ste, DR_STE_SIZE_CTRL,
0, last_ste->hw_ste,
ste_info_last, send_list, true);
@@ -110,10 +110,14 @@ dr_rule_handle_one_ste_in_update_list(struct mlx5dr_ste_send_info *ste_info,
ste_info->size, ste_info->offset);
if (ret)
goto out;
- /* Copy data to ste, only reduced size, the last 16B (mask)
+
+ /* Copy data to ste, only reduced size or control, the last 16B (mask)
* is already written to the hw.
*/
- memcpy(ste_info->ste->hw_ste, ste_info->data, DR_STE_SIZE_REDUCED);
+ if (ste_info->size == DR_STE_SIZE_CTRL)
+ memcpy(ste_info->ste->hw_ste, ste_info->data, DR_STE_SIZE_CTRL);
+ else
+ memcpy(ste_info->ste->hw_ste, ste_info->data, DR_STE_SIZE_REDUCED);
out:
kfree(ste_info);
@@ -456,7 +460,7 @@ dr_rule_rehash_htbl(struct mlx5dr_rule *rule,
ste_to_update = cur_htbl->pointing_ste;
}
- mlx5dr_send_fill_and_append_ste_send_info(ste_to_update, DR_STE_SIZE_REDUCED,
+ mlx5dr_send_fill_and_append_ste_send_info(ste_to_update, DR_STE_SIZE_CTRL,
0, ste_to_update->hw_ste, ste_info,
update_list, false);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
index 0f318f409c91..e21b61030e35 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
@@ -264,7 +264,7 @@ static void dr_ste_remove_middle_ste(struct mlx5dr_ste_ctx *ste_ctx,
miss_addr = ste_ctx->get_miss_addr(ste->hw_ste);
ste_ctx->set_miss_addr(prev_ste->hw_ste, miss_addr);
- mlx5dr_send_fill_and_append_ste_send_info(prev_ste, DR_STE_SIZE_REDUCED, 0,
+ mlx5dr_send_fill_and_append_ste_send_info(prev_ste, DR_STE_SIZE_CTRL, 0,
prev_ste->hw_ste, ste_info,
send_ste_list, true /* Copy data*/);
--
2.29.2
next prev parent reply other threads:[~2021-01-30 9:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-30 2:26 [pull request][net-next 00/11] mlx5 SW steering for ConnectX-6DX Saeed Mahameed
2021-01-30 2:26 ` [net-next 01/11] net/mlx5: DR, Fix potential shift wrapping of 32-bit value Saeed Mahameed
2021-02-02 3:00 ` patchwork-bot+netdevbpf
2021-01-30 2:26 ` [net-next 02/11] net/mlx5: DR, Add match STEv1 structs to ifc Saeed Mahameed
2021-01-30 2:26 ` [net-next 03/11] net/mlx5: DR, Add HW STEv1 match logic Saeed Mahameed
2021-01-30 2:26 ` [net-next 04/11] net/mlx5: DR, Allow native protocol support for HW STEv1 Saeed Mahameed
2021-01-30 2:26 ` [net-next 05/11] net/mlx5: DR, Add STEv1 setters and getters Saeed Mahameed
2021-01-30 2:26 ` [net-next 06/11] net/mlx5: DR, Add STEv1 action apply logic Saeed Mahameed
2021-01-30 2:26 ` [net-next 07/11] net/mlx5: DR, Add STEv1 modify header logic Saeed Mahameed
2021-01-30 2:26 ` Saeed Mahameed [this message]
2021-01-30 2:26 ` [net-next 09/11] net/mlx5: DR, Use HW specific logic API when writing STE Saeed Mahameed
2021-01-30 2:26 ` [net-next 10/11] net/mlx5: DR, Copy all 64B whenever replacing STE in the head of miss-list Saeed Mahameed
2021-01-30 2:26 ` [net-next 11/11] net/mlx5: DR, Allow SW steering for sw_owner_v2 devices Saeed Mahameed
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