From: Saeed Mahameed <saeed@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>
Cc: netdev@vger.kernel.org, linux-rdma@vger.kernel.org,
Maor Gottlieb <maorg@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>
Subject: [net 13/18] RDMA/mlx5: Fix timestamp default mode
Date: Wed, 10 Mar 2021 11:03:37 -0800 [thread overview]
Message-ID: <20210310190342.238957-14-saeed@kernel.org> (raw)
In-Reply-To: <20210310190342.238957-1-saeed@kernel.org>
From: Maor Gottlieb <maorg@nvidia.com>
1. Don't set the ts_format bit to default when it reserved - device is
running in the old mode (free running).
2. XRC doesn't have a CQ therefore the ts format in the QP
context should be default / free running.
3. Set ts_format to WQ.
Fixes: 2fe8d4b87802 ("RDMA/mlx5: Fail QP creation if the device can not support the CQE TS")
Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
drivers/infiniband/hw/mlx5/qp.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c
index ec4b3f6a8222..f5a52a6fae43 100644
--- a/drivers/infiniband/hw/mlx5/qp.c
+++ b/drivers/infiniband/hw/mlx5/qp.c
@@ -1078,7 +1078,7 @@ static int _create_kernel_qp(struct mlx5_ib_dev *dev,
qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
MLX5_SET(qpc, qpc, uar_page, uar_index);
- MLX5_SET(qpc, qpc, ts_format, MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT);
+ MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev));
MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
/* Set "fast registration enabled" for all kernel QPs */
@@ -1188,7 +1188,8 @@ static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq)
}
return MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING;
}
- return MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;
+ return fr_supported ? MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING :
+ MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;
}
static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq)
@@ -1206,7 +1207,8 @@ static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq)
}
return MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING;
}
- return MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;
+ return fr_supported ? MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING :
+ MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;
}
static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq,
@@ -1217,7 +1219,8 @@ static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq,
MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING ||
MLX5_CAP_ROCE(dev->mdev, qp_ts_format) ==
MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME;
- int ts_format = MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
+ int ts_format = fr_supported ? MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
+ MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
if (recv_cq &&
recv_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)
@@ -1930,6 +1933,7 @@ static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
MLX5_SET(qpc, qpc, cd_slave_receive, 1);
+ MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev));
MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
MLX5_SET(qpc, qpc, no_sq, 1);
MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
@@ -4873,6 +4877,7 @@ static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
struct mlx5_ib_dev *dev;
int has_net_offloads;
__be64 *rq_pas0;
+ int ts_format;
void *in;
void *rqc;
void *wq;
@@ -4881,6 +4886,10 @@ static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
dev = to_mdev(pd->device);
+ ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq));
+ if (ts_format < 0)
+ return ts_format;
+
inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
in = kvzalloc(inlen, GFP_KERNEL);
if (!in)
@@ -4890,6 +4899,7 @@ static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
MLX5_SET(rqc, rqc, mem_rq_type,
MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
+ MLX5_SET(rqc, rqc, ts_format, ts_format);
MLX5_SET(rqc, rqc, user_index, rwq->user_index);
MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
--
2.29.2
next prev parent reply other threads:[~2021-03-10 19:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 19:03 [pull request][net 00/18] mlx5 fixes 2021-03-10 Saeed Mahameed
2021-03-10 19:03 ` [net 01/18] net/mlx5e: Enforce minimum value check for ICOSQ size Saeed Mahameed
2021-03-10 23:40 ` patchwork-bot+netdevbpf
2021-03-10 19:03 ` [net 02/18] net/mlx5e: RX, Mind the MPWQE gaps when calculating offsets Saeed Mahameed
2021-03-10 19:03 ` [net 03/18] net/mlx5e: Accumulate port PTP TX stats with other channels stats Saeed Mahameed
2021-03-10 19:03 ` [net 04/18] net/mlx5e: Set PTP channel pointer explicitly to NULL Saeed Mahameed
2021-03-10 19:03 ` [net 05/18] net/mlx5e: When changing XDP program without reset, take refs for XSK RQs Saeed Mahameed
2021-03-10 19:03 ` [net 06/18] net/mlx5e: Revert parameters on errors when changing PTP state without reset Saeed Mahameed
2021-03-10 19:03 ` [net 07/18] net/mlx5e: Don't match on Geneve options in case option masks are all zero Saeed Mahameed
2021-03-10 19:03 ` [net 08/18] net/mlx5: Fix turn-off PPS command Saeed Mahameed
2021-03-10 19:03 ` [net 09/18] net/mlx5e: Check correct ip_version in decapsulation route resolution Saeed Mahameed
2021-03-10 19:03 ` [net 10/18] net/mlx5: Disable VF tunnel TX offload if ignore_flow_level isn't supported Saeed Mahameed
2021-03-10 19:03 ` [net 11/18] net/mlx5e: Fix error flow in change profile Saeed Mahameed
2021-03-10 19:03 ` [net 12/18] net/mlx5: Set QP timestamp mode to default Saeed Mahameed
2021-03-10 19:03 ` Saeed Mahameed [this message]
2021-03-10 19:25 ` [net 13/18] RDMA/mlx5: Fix timestamp default mode Jason Gunthorpe
2021-03-11 8:58 ` Leon Romanovsky
2021-03-10 19:03 ` [net 14/18] net/mlx5e: E-switch, Fix rate calculation division Saeed Mahameed
2021-03-10 19:03 ` [net 15/18] net/mlx5: SF, Correct vhca context size Saeed Mahameed
2021-03-10 19:03 ` [net 16/18] net/mlx5: SF: Fix memory leak of work item Saeed Mahameed
2021-03-10 19:03 ` [net 17/18] net/mlx5: SF: Fix error flow of SFs allocation flow Saeed Mahameed
2021-03-10 19:03 ` [net 18/18] net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter Saeed Mahameed
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