From: Saeed Mahameed <saeed@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>
Cc: netdev@vger.kernel.org, linux-rdma@vger.kernel.org,
Tariq Toukan <tariqt@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>
Subject: [net 02/18] net/mlx5e: RX, Mind the MPWQE gaps when calculating offsets
Date: Wed, 10 Mar 2021 11:03:26 -0800 [thread overview]
Message-ID: <20210310190342.238957-3-saeed@kernel.org> (raw)
In-Reply-To: <20210310190342.238957-1-saeed@kernel.org>
From: Tariq Toukan <tariqt@nvidia.com>
Since cited patch, MLX5E_REQUIRED_WQE_MTTS is not a power of two.
Hence, usage of MLX5E_LOG_ALIGNED_MPWQE_PPW should be replaced,
as it lost some accuracy. Use the designated macro to calculate
the number of required MTTs.
This makes sure the solution in cited patch works properly.
While here, un-inline mlx5e_get_mpwqe_offset(), and remove the
unused RQ parameter.
Fixes: c3c9402373fe ("net/mlx5e: Add resiliency in Striding RQ mode for packets larger than MTU")
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/en.h | 7 ++++---
drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 6 +++---
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 4 ++--
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index 7435fe6829b6..304b296fe8b9 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -92,14 +92,15 @@ struct page_pool;
MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
#define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
-#define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
+#define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8))
+#define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2)
+#define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts)))
/* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between
* WQEs, This page will absorb write overflow by the hardware, when
* receiving packets larger than MTU. These oversize packets are
* dropped by the driver at a later stage.
*/
-#define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE + 1, 8))
-#define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
+#define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))
#define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
#define MLX5E_MAX_RQ_NUM_MTTS \
((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 5c8ffa8da6f0..831f5495ff39 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -334,9 +334,9 @@ static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq
rq->wqe_overflow.addr);
}
-static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
+static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
{
- return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
+ return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
}
static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
@@ -577,7 +577,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c,
mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
u32 byte_count =
rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
- u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
+ u64 dma_offset = mlx5e_get_mpwqe_offset(i);
wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
wqe->data[0].byte_count = cpu_to_be32(byte_count);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
index 1b6ad94ebb10..249d8905e644 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
@@ -500,7 +500,6 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
struct mlx5e_icosq *sq = rq->icosq;
struct mlx5_wq_cyc *wq = &sq->wq;
struct mlx5e_umr_wqe *umr_wqe;
- u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
u16 pi;
int err;
int i;
@@ -531,7 +530,8 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
umr_wqe->ctrl.opmod_idx_opcode =
cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
MLX5_OPCODE_UMR);
- umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
+ umr_wqe->uctrl.xlt_offset =
+ cpu_to_be16(MLX5_ALIGNED_MTTS_OCTW(MLX5E_REQUIRED_MTTS(ix)));
sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {
.wqe_type = MLX5E_ICOSQ_WQE_UMR_RX,
--
2.29.2
next prev parent reply other threads:[~2021-03-10 19:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 19:03 [pull request][net 00/18] mlx5 fixes 2021-03-10 Saeed Mahameed
2021-03-10 19:03 ` [net 01/18] net/mlx5e: Enforce minimum value check for ICOSQ size Saeed Mahameed
2021-03-10 23:40 ` patchwork-bot+netdevbpf
2021-03-10 19:03 ` Saeed Mahameed [this message]
2021-03-10 19:03 ` [net 03/18] net/mlx5e: Accumulate port PTP TX stats with other channels stats Saeed Mahameed
2021-03-10 19:03 ` [net 04/18] net/mlx5e: Set PTP channel pointer explicitly to NULL Saeed Mahameed
2021-03-10 19:03 ` [net 05/18] net/mlx5e: When changing XDP program without reset, take refs for XSK RQs Saeed Mahameed
2021-03-10 19:03 ` [net 06/18] net/mlx5e: Revert parameters on errors when changing PTP state without reset Saeed Mahameed
2021-03-10 19:03 ` [net 07/18] net/mlx5e: Don't match on Geneve options in case option masks are all zero Saeed Mahameed
2021-03-10 19:03 ` [net 08/18] net/mlx5: Fix turn-off PPS command Saeed Mahameed
2021-03-10 19:03 ` [net 09/18] net/mlx5e: Check correct ip_version in decapsulation route resolution Saeed Mahameed
2021-03-10 19:03 ` [net 10/18] net/mlx5: Disable VF tunnel TX offload if ignore_flow_level isn't supported Saeed Mahameed
2021-03-10 19:03 ` [net 11/18] net/mlx5e: Fix error flow in change profile Saeed Mahameed
2021-03-10 19:03 ` [net 12/18] net/mlx5: Set QP timestamp mode to default Saeed Mahameed
2021-03-10 19:03 ` [net 13/18] RDMA/mlx5: Fix timestamp default mode Saeed Mahameed
2021-03-10 19:25 ` Jason Gunthorpe
2021-03-11 8:58 ` Leon Romanovsky
2021-03-10 19:03 ` [net 14/18] net/mlx5e: E-switch, Fix rate calculation division Saeed Mahameed
2021-03-10 19:03 ` [net 15/18] net/mlx5: SF, Correct vhca context size Saeed Mahameed
2021-03-10 19:03 ` [net 16/18] net/mlx5: SF: Fix memory leak of work item Saeed Mahameed
2021-03-10 19:03 ` [net 17/18] net/mlx5: SF: Fix error flow of SFs allocation flow Saeed Mahameed
2021-03-10 19:03 ` [net 18/18] net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter Saeed Mahameed
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