[PATCH net-next 0/7] net: phy: marvell10g updates

[PATCH net-next 0/7] net: phy: marvell10g updates

[Marek Behún]

Here are some updates for marvell10g PHY driver.

Marek Behún (7):
  net: phy: marvell10g: rename register
  net: phy: marvell10g: fix typo
  net: phy: marvell10g: allow 5gabse-r and usxgmii
  net: phy: marvell10g: add MACTYPE definitions for 88X3310/88X3310P
  net: phy: marvell10g: save MACTYPE instead of rate_matching boolean
  net: phy: marvell10g: support more rate matching modes
  net: phy: marvell10g: support other MACTYPEs

 drivers/net/phy/marvell10g.c | 102 +++++++++++++++++++++++------------
 1 file changed, 67 insertions(+), 35 deletions(-)

-- 
2.26.2

[PATCH net-next 1/7] net: phy: marvell10g: rename register

[Marek Behún]

The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index b1bb9b8e1e4e..96c081a7ec54 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -80,8 +80,8 @@ enum {
 	MV_V2_PORT_CTRL		= 0xf001,
 	MV_V2_PORT_CTRL_SWRST	= BIT(15),
 	MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
-	MV_V2_PORT_MAC_TYPE_MASK = 0x7,
-	MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
+	MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
+	MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
 	/* Temperature control/read registers (88X3310 only) */
 	MV_V2_TEMP_CTRL		= 0xf08a,
 	MV_V2_TEMP_CTRL_MASK	= 0xc000,
@@ -477,8 +477,8 @@ static int mv3310_config_init(struct phy_device *phydev)
 	val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
 	if (val < 0)
 		return val;
-	priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
-			MV_V2_PORT_MAC_TYPE_RATE_MATCH);
+	priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
+			MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
 
 	/* Enable EDPD mode - saving 600mW */
 	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
-- 
2.26.2

[PATCH net-next 2/7] net: phy: marvell10g: fix typo

[Marek Behún]

This space should be a tab instead.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 96c081a7ec54..567e7900e5b8 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -79,7 +79,7 @@ enum {
 	/* Vendor2 MMD registers */
 	MV_V2_PORT_CTRL		= 0xf001,
 	MV_V2_PORT_CTRL_SWRST	= BIT(15),
-	MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+	MV_V2_PORT_CTRL_PWRDOWN	= BIT(11),
 	MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
 	MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
 	/* Temperature control/read registers (88X3310 only) */
-- 
2.26.2

[PATCH net-next 3/7] net: phy: marvell10g: allow 5gabse-r and usxgmii

[Marek Behún]

This modes are also supported by this PHYs.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 567e7900e5b8..70639b9393f3 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -462,9 +462,11 @@ static int mv3310_config_init(struct phy_device *phydev)
 	/* Check that the PHY interface type is compatible */
 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
 	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+	    phydev->interface != PHY_INTERFACE_MODE_5GBASER &&
 	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
 	    phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
-	    phydev->interface != PHY_INTERFACE_MODE_10GBASER)
+	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
+	    phydev->interface != PHY_INTERFACE_MODE_USXGMII)
 		return -ENODEV;
 
 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
@@ -611,6 +613,9 @@ static void mv3310_update_interface(struct phy_device *phydev)
 		case SPEED_10000:
 			phydev->interface = PHY_INTERFACE_MODE_10GBASER;
 			break;
+		case SPEED_5000:
+			phydev->interface = PHY_INTERFACE_MODE_5GBASER;
+			break;
 		case SPEED_2500:
 			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 			break;
-- 
2.26.2

[PATCH net-next 4/7] net: phy: marvell10g: add MACTYPE definitions for 88X3310/88X3310P

[Marek Behún]

Add all MACTYPE definitions for 88X3310/88X3310P.

In order to have consistent naming, rename
MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to
MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 70639b9393f3..46e853f2d41b 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -80,8 +80,15 @@ enum {
 	MV_V2_PORT_CTRL		= 0xf001,
 	MV_V2_PORT_CTRL_SWRST	= BIT(15),
 	MV_V2_PORT_CTRL_PWRDOWN	= BIT(11),
-	MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
-	MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
+	MV_V2_PORT_CTRL_MACTYPE_MASK			= 0x7,
+	MV_V2_PORT_CTRL_MACTYPE_RXAUI			= 0x0,
+	MV_V2_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH		= 0x1,
+	MV_V2_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH	= 0x2,
+	MV_V2_PORT_CTRL_MACTYPE_XAUI			= 0x3,
+	MV_V2_PORT_CTRL_MACTYPE_10GBASER		= 0x4,
+	MV_V2_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN	= 0x5,
+	MV_V2_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH	= 0x6,
+	MV_V2_PORT_CTRL_MACTYPE_USXGMII			= 0x7,
 	/* Temperature control/read registers (88X3310 only) */
 	MV_V2_TEMP_CTRL		= 0xf08a,
 	MV_V2_TEMP_CTRL_MASK	= 0xc000,
@@ -480,7 +487,7 @@ static int mv3310_config_init(struct phy_device *phydev)
 	if (val < 0)
 		return val;
 	priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
-			MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
+			MV_V2_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH);
 
 	/* Enable EDPD mode - saving 600mW */
 	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
-- 
2.26.2

Re: [PATCH net-next 4/7] net: phy: marvell10g: add MACTYPE definitions for 88X3310/88X3310P

[Russell King - ARM Linux admin]

On Wed, Mar 24, 2021 at 05:50:20PM +0100, Marek Behún wrote:
> Add all MACTYPE definitions for 88X3310/88X3310P.
> 
> In order to have consistent naming, rename
> MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to
> MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH.

We probably ought to note that the 88x3310 and 88x3340 will be detected
by this driver, but have different MACTYPE definitions.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 4/7] net: phy: marvell10g: add MACTYPE definitions for 88X3310/88X3310P

[Marek Behún]

On Wed, 24 Mar 2021 16:58:36 +0000
Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:

> On Wed, Mar 24, 2021 at 05:50:20PM +0100, Marek Behún wrote:
> > Add all MACTYPE definitions for 88X3310/88X3310P.
> > 
> > In order to have consistent naming, rename
> > MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to
> > MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH.  
> 
> We probably ought to note that the 88x3310 and 88x3340 will be detected
> by this driver, but have different MACTYPE definitions.

Is 88X3340 supported? The drivers structure only defines for
 .phy_id = MARVELL_PHY_ID_88X3310
Do 88X3310 and 3340 have the same PHY_ID ?

Also these registers are different for 88E2110, and the register
which contains MACTYPE has a different address. Yes, I want to do this,
but in another series, because I don't have the board with 88E2210 now.

Marek

Re: [PATCH net-next 4/7] net: phy: marvell10g: add MACTYPE definitions for 88X3310/88X3310P

[Russell King - ARM Linux admin]

On Wed, Mar 24, 2021 at 06:09:09PM +0000, Marek Behún wrote:
> On Wed, 24 Mar 2021 16:58:36 +0000
> Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:
> 
> > On Wed, Mar 24, 2021 at 05:50:20PM +0100, Marek Behún wrote:
> > > Add all MACTYPE definitions for 88X3310/88X3310P.
> > > 
> > > In order to have consistent naming, rename
> > > MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to
> > > MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH.  
> > 
> > We probably ought to note that the 88x3310 and 88x3340 will be detected
> > by this driver, but have different MACTYPE definitions.
> 
> Is 88X3340 supported? The drivers structure only defines for
>  .phy_id = MARVELL_PHY_ID_88X3310
> Do 88X3310 and 3340 have the same PHY_ID ?

Yes they do. I believe they can be distinguished by bit 3,
conventionally part of the PHY revision.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

[PATCH net-next 5/7] net: phy: marvell10g: save MACTYPE instead of rate_matching boolean

[Marek Behún]

Save MACTYPE instead of rate_matching boolean. We will need this for
other configurations.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 46e853f2d41b..b4f9831b4db6 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -100,7 +100,7 @@ enum {
 
 struct mv3310_priv {
 	u32 firmware_ver;
-	bool rate_match;
+	u8 mactype;
 
 	struct device *hwmon_dev;
 	char *hwmon_name;
@@ -486,8 +486,7 @@ static int mv3310_config_init(struct phy_device *phydev)
 	val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
 	if (val < 0)
 		return val;
-	priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
-			MV_V2_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH);
+	priv->mactype = val & MV_V2_PORT_CTRL_MACTYPE_MASK;
 
 	/* Enable EDPD mode - saving 600mW */
 	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
@@ -601,7 +600,7 @@ static void mv3310_update_interface(struct phy_device *phydev)
 	 * 10Gb. The PHY adapts the rate to actual wire speed with help of
 	 * internal 16KB buffer.
 	 */
-	if (priv->rate_match) {
+	if (priv->mactype == MV_V2_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) {
 		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
 		return;
 	}
-- 
2.26.2

Re: [PATCH net-next 5/7] net: phy: marvell10g: save MACTYPE instead of rate_matching boolean

[Russell King - ARM Linux admin]

On Wed, Mar 24, 2021 at 05:50:21PM +0100, Marek Behún wrote:
> Save MACTYPE instead of rate_matching boolean. We will need this for
> other configurations.

This could lead us to having to test for multiple different mactype
values depending on the PHY type in mv3310_update_interface() which
is something I wanted to avoid.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 5/7] net: phy: marvell10g: save MACTYPE instead of rate_matching boolean

[Marek Behún]

On Wed, 24 Mar 2021 16:59:46 +0000
Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:

> On Wed, Mar 24, 2021 at 05:50:21PM +0100, Marek Behún wrote:
> > Save MACTYPE instead of rate_matching boolean. We will need this for
> > other configurations.  
> 
> This could lead us to having to test for multiple different mactype
> values depending on the PHY type in mv3310_update_interface() which
> is something I wanted to avoid.
> 

This is currently done in patches 6/7 and 7/7...

Either we do this this way, or we save both members
  bool rate_matching;
  phy_interface_t interface10g;
in order not to do this always in mv3310_update_interface().

I guess I am going to change it.

Marek

[PATCH net-next 6/7] net: phy: marvell10g: support more rate matching modes

[Marek Behún]

The 88X3310P supports rate matching mode also for XAUI and RXAUI.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index b4f9831b4db6..c764795a142a 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -596,13 +596,22 @@ static void mv3310_update_interface(struct phy_device *phydev)
 {
 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
 
-	/* In "XFI with Rate Matching" mode the PHY interface is fixed at
-	 * 10Gb. The PHY adapts the rate to actual wire speed with help of
+	/* In all of the "* with Rate Matching" modes the PHY interface is fixed
+	 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
 	 * internal 16KB buffer.
 	 */
-	if (priv->mactype == MV_V2_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) {
+	switch (priv->mactype) {
+	case MV_V2_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH:
 		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
 		return;
+	case MV_V2_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH:
+		phydev->interface = PHY_INTERFACE_MODE_XAUI;
+		return;
+	case MV_V2_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH:
+		phydev->interface = PHY_INTERFACE_MODE_RXAUI;
+		return;
+	default:
+		break;
 	}
 
 	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
-- 
2.26.2

[PATCH net-next 7/7] net: phy: marvell10g: support other MACTYPEs

[Marek Behún]

Currently the only "changing" MACTYPE we support is when the PHY changes
between
  10gbase-r / 5gbase-r / 2500base-x / sgmii

Add support for
  xaui / 5gbase-r / 2500base-x / sgmii
  rxaui / 5gbase-r / 2500base-x / sgmii

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 70 +++++++++++++++++++++---------------
 1 file changed, 41 insertions(+), 29 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index c764795a142a..a0fc74456d32 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -595,6 +595,10 @@ static int mv3310_aneg_done(struct phy_device *phydev)
 static void mv3310_update_interface(struct phy_device *phydev)
 {
 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+	phy_interface_t interface10g;
+
+	if (!phydev->link)
+		return;
 
 	/* In all of the "* with Rate Matching" modes the PHY interface is fixed
 	 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
@@ -610,38 +614,46 @@ static void mv3310_update_interface(struct phy_device *phydev)
 	case MV_V2_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH:
 		phydev->interface = PHY_INTERFACE_MODE_RXAUI;
 		return;
-	default:
+	case MV_V2_PORT_CTRL_MACTYPE_USXGMII:
+		phydev->interface = PHY_INTERFACE_MODE_USXGMII;
+		return;
+	case MV_V2_PORT_CTRL_MACTYPE_10GBASER:
+	case MV_V2_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN:
+		interface10g = PHY_INTERFACE_MODE_10GBASER;
 		break;
+	case MV_V2_PORT_CTRL_MACTYPE_XAUI:
+		interface10g = PHY_INTERFACE_MODE_XAUI;
+		break;
+	case MV_V2_PORT_CTRL_MACTYPE_RXAUI:
+		interface10g = PHY_INTERFACE_MODE_RXAUI;
+		break;
+	default:
+		unreachable();
 	}
 
-	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
-	     phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
-	     phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
-	    phydev->link) {
-		/* The PHY automatically switches its serdes interface (and
-		 * active PHYXS instance) between Cisco SGMII, 10GBase-R and
-		 * 2500BaseX modes according to the speed.  Florian suggests
-		 * setting phydev->interface to communicate this to the MAC.
-		 * Only do this if we are already in one of the above modes.
-		 */
-		switch (phydev->speed) {
-		case SPEED_10000:
-			phydev->interface = PHY_INTERFACE_MODE_10GBASER;
-			break;
-		case SPEED_5000:
-			phydev->interface = PHY_INTERFACE_MODE_5GBASER;
-			break;
-		case SPEED_2500:
-			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-			break;
-		case SPEED_1000:
-		case SPEED_100:
-		case SPEED_10:
-			phydev->interface = PHY_INTERFACE_MODE_SGMII;
-			break;
-		default:
-			break;
-		}
+	/* The PHY automatically switches its serdes interface (and active PHYXS
+	 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
+	 * xaui / rxaui modes according to the speed.
+	 * Florian suggests setting phydev->interface to communicate this to the
+	 * MAC. Only do this if we are already in one of the above modes.
+	 */
+	switch (phydev->speed) {
+	case SPEED_10000:
+		phydev->interface = interface10g;
+		break;
+	case SPEED_5000:
+		phydev->interface = PHY_INTERFACE_MODE_5GBASER;
+		break;
+	case SPEED_2500:
+		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+		break;
+	case SPEED_1000:
+	case SPEED_100:
+	case SPEED_10:
+		phydev->interface = PHY_INTERFACE_MODE_SGMII;
+		break;
+	default:
+		break;
 	}
 }
 
-- 
2.26.2