[PATCH net-next v2 00/12] net: phy: marvell10g updates

[PATCH net-next v2 00/12] net: phy: marvell10g updates

[Marek Behún]

Here are some updates for marvell10g PHY driver.

Changes since v1:
- added various MACTYPEs support also for 88E21XX
- differentiate between specific models with same PHY_ID
- better check for compatible interface
- print exact model

Marek Behún (12):
  net: phy: marvell10g: rename register
  net: phy: marvell10g: fix typo
  net: phy: marvell10g: allow 5gbase-r and usxgmii
  net: phy: marvell10g: indicate 88X33X0 only port control registers
  net: phy: marvell10g: add MACTYPE definitions for 88X33X0/88X33X0P
  net: phy: marvell10g: add MACTYPE definitions for 88E21XX
  net: phy: marvell10g: add code to determine number of ports
  net: phy: marvell10g: support all rate matching modes
  net: phy: marvell10g: support other MACTYPEs
  net: phy: add constants for 2.5G and 5G speed in PCS speed register
  net: phy: marvell10g: print exact model
  net: phy: marvell10g: better check for compatible interface

 drivers/net/phy/marvell10g.c | 262 +++++++++++++++++++++++++++++------
 include/uapi/linux/mdio.h    |   2 +
 2 files changed, 220 insertions(+), 44 deletions(-)

-- 
2.26.2

[PATCH net-next v2 01/12] net: phy: marvell10g: rename register

[Marek Behún]

The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 74b64e52ffa2..9b514124af0d 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -80,8 +80,8 @@ enum {
 	MV_V2_PORT_CTRL		= 0xf001,
 	MV_V2_PORT_CTRL_SWRST	= BIT(15),
 	MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
-	MV_V2_PORT_MAC_TYPE_MASK = 0x7,
-	MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
+	MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
+	MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
 	/* Temperature control/read registers (88X3310 only) */
 	MV_V2_TEMP_CTRL		= 0xf08a,
 	MV_V2_TEMP_CTRL_MASK	= 0xc000,
@@ -477,8 +477,8 @@ static int mv3310_config_init(struct phy_device *phydev)
 	val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
 	if (val < 0)
 		return val;
-	priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
-			MV_V2_PORT_MAC_TYPE_RATE_MATCH);
+	priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
+			MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
 
 	/* Enable EDPD mode - saving 600mW */
 	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
-- 
2.26.2

[PATCH net-next v2 02/12] net: phy: marvell10g: fix typo

[Marek Behún]

This space should be a tab instead.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9b514124af0d..f2f0da9717be 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -79,7 +79,7 @@ enum {
 	/* Vendor2 MMD registers */
 	MV_V2_PORT_CTRL		= 0xf001,
 	MV_V2_PORT_CTRL_SWRST	= BIT(15),
-	MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
+	MV_V2_PORT_CTRL_PWRDOWN	= BIT(11),
 	MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
 	MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
 	/* Temperature control/read registers (88X3310 only) */
-- 
2.26.2

[PATCH net-next v2 03/12] net: phy: marvell10g: allow 5gbase-r and usxgmii

[Marek Behún]

This modes are also supported by this PHYs.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f2f0da9717be..881a0717846e 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -462,9 +462,11 @@ static int mv3310_config_init(struct phy_device *phydev)
 	/* Check that the PHY interface type is compatible */
 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
 	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+	    phydev->interface != PHY_INTERFACE_MODE_5GBASER &&
 	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
 	    phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
-	    phydev->interface != PHY_INTERFACE_MODE_10GBASER)
+	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
+	    phydev->interface != PHY_INTERFACE_MODE_USXGMII)
 		return -ENODEV;
 
 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
@@ -599,6 +601,7 @@ static void mv3310_update_interface(struct phy_device *phydev)
 
 	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
 	     phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
+	     phydev->interface == PHY_INTERFACE_MODE_5GBASER ||
 	     phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
 	    phydev->link) {
 		/* The PHY automatically switches its serdes interface (and
@@ -611,6 +614,9 @@ static void mv3310_update_interface(struct phy_device *phydev)
 		case SPEED_10000:
 			phydev->interface = PHY_INTERFACE_MODE_10GBASER;
 			break;
+		case SPEED_5000:
+			phydev->interface = PHY_INTERFACE_MODE_5GBASER;
+			break;
 		case SPEED_2500:
 			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 			break;
-- 
2.26.2

[PATCH net-next v2 04/12] net: phy: marvell10g: indicate 88X33X0 only port control registers

[Marek Behún]

Indicate via register names registers that are only valid for 88X33X0,
not for 88E21X0.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 881a0717846e..7552a658a513 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -78,10 +78,10 @@ enum {
 
 	/* Vendor2 MMD registers */
 	MV_V2_PORT_CTRL		= 0xf001,
-	MV_V2_PORT_CTRL_SWRST	= BIT(15),
-	MV_V2_PORT_CTRL_PWRDOWN	= BIT(11),
-	MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
-	MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
+	MV_V2_PORT_CTRL_PWRDOWN			= BIT(11),
+	MV_V2_33X0_PORT_CTRL_SWRST		= BIT(15),
+	MV_V2_33X0_PORT_CTRL_MACTYPE_MASK	= 0x7,
+	MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH	= 0x6,
 	/* Temperature control/read registers (88X3310 only) */
 	MV_V2_TEMP_CTRL		= 0xf08a,
 	MV_V2_TEMP_CTRL_MASK	= 0xc000,
@@ -268,7 +268,7 @@ static int mv3310_power_up(struct phy_device *phydev)
 		return ret;
 
 	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
-				MV_V2_PORT_CTRL_SWRST);
+				MV_V2_33X0_PORT_CTRL_SWRST);
 }
 
 static int mv3310_reset(struct phy_device *phydev, u32 unit)
@@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev)
 	val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
 	if (val < 0)
 		return val;
-	priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
-			MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
+	priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
+			MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH);
 
 	/* Enable EDPD mode - saving 600mW */
 	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
-- 
2.26.2

[PATCH net-next v2 05/12] net: phy: marvell10g: add MACTYPE definitions for 88X33X0/88X33X0P

[Marek Behún]

Add all MACTYPE definitions for 88X3310, 88X3310P, 88X3340 and 88X3340P.

In order to have consistent naming, rename
MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH to
MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 7552a658a513..7d9a45437b69 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -78,10 +78,18 @@ enum {
 
 	/* Vendor2 MMD registers */
 	MV_V2_PORT_CTRL		= 0xf001,
-	MV_V2_PORT_CTRL_PWRDOWN			= BIT(11),
-	MV_V2_33X0_PORT_CTRL_SWRST		= BIT(15),
-	MV_V2_33X0_PORT_CTRL_MACTYPE_MASK	= 0x7,
-	MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH	= 0x6,
+	MV_V2_PORT_CTRL_PWRDOWN					= BIT(11),
+	MV_V2_33X0_PORT_CTRL_SWRST				= BIT(15),
+	MV_V2_33X0_PORT_CTRL_MACTYPE_MASK			= 0x7,
+	MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI			= 0x0,
+	MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH		= 0x1,
+	MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN		= 0x1,
+	MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH		= 0x2,
+	MV_V2_3310_PORT_CTRL_MACTYPE_XAUI			= 0x3,
+	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER			= 0x4,
+	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN	= 0x5,
+	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH	= 0x6,
+	MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII			= 0x7,
 	/* Temperature control/read registers (88X3310 only) */
 	MV_V2_TEMP_CTRL		= 0xf08a,
 	MV_V2_TEMP_CTRL_MASK	= 0xc000,
@@ -480,7 +488,7 @@ static int mv3310_config_init(struct phy_device *phydev)
 	if (val < 0)
 		return val;
 	priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
-			MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH);
+			MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH);
 
 	/* Enable EDPD mode - saving 600mW */
 	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
-- 
2.26.2

[PATCH net-next v2 06/12] net: phy: marvell10g: add MACTYPE definitions for 88E21XX

[Marek Behún]

Add all MACTYPE definitions for 88E2110, 88E2180, 88E2111 and 88E2181.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 7d9a45437b69..556c9b43860e 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -35,6 +35,15 @@
 enum {
 	MV_PMA_FW_VER0		= 0xc011,
 	MV_PMA_FW_VER1		= 0xc012,
+	MV_PMA_21X0_PORT_CTRL	= 0xc04a,
+	MV_PMA_21X0_PORT_CTRL_SWRST				= BIT(15),
+	MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK			= 0x7,
+	MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII			= 0x0,
+	MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII			= 0x1,
+	MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII			= 0x2,
+	MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER			= 0x4,
+	MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN	= 0x5,
+	MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH	= 0x6,
 	MV_PMA_BOOT		= 0xc050,
 	MV_PMA_BOOT_FATAL	= BIT(0),
 
-- 
2.26.2

[PATCH net-next v2 07/12] net: phy: marvell10g: add code to determine number of ports

[Marek Behún]

Add code to determine number of ports, from which we differentiate
88E211X from 88E218X and 88X3310 from 88X3340.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 44 +++++++++++++++++++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 556c9b43860e..b49cff895cdd 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -78,6 +78,10 @@ enum {
 	/* Temperature read register (88E2110 only) */
 	MV_PCS_TEMP		= 0x8042,
 
+	MV_PCS_ID		= 0xd00d,
+	MV_PCS_ID_NPORTS_MASK	= 0x0380,
+	MV_PCS_ID_NPORTS_SHIFT	= 7,
+
 	/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
 	 * registers appear to set themselves to the 0x800X when AN is
 	 * restarted, but status registers appear readable from either.
@@ -108,7 +112,17 @@ enum {
 	MV_V2_TEMP_UNKNOWN	= 0x9600, /* unknown function */
 };
 
+enum mv3310_model {
+	MV_MODEL_NA = 0,
+	MV_MODEL_88E211X,
+	MV_MODEL_88E218X,
+	MV_MODEL_88X3310,
+	MV_MODEL_88X3340,
+};
+
 struct mv3310_priv {
+	enum mv3310_model model;
+
 	u32 firmware_ver;
 	bool rate_match;
 
@@ -382,7 +396,7 @@ static int mv3310_probe(struct phy_device *phydev)
 {
 	struct mv3310_priv *priv;
 	u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
-	int ret;
+	int ret, nports;
 
 	if (!phydev->is_c45 ||
 	    (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
@@ -420,6 +434,34 @@ static int mv3310_probe(struct phy_device *phydev)
 		    priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
 		    (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
 
+	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_ID);
+	if (ret < 0)
+		return ret;
+
+	nports = ((ret & MV_PCS_ID_NPORTS_MASK) >> MV_PCS_ID_NPORTS_SHIFT) + 1;
+
+	switch (phydev->drv->phy_id) {
+	case MARVELL_PHY_ID_88X3310:
+		if (nports == 4)
+			priv->model = MV_MODEL_88X3340;
+		else if (nports == 1)
+			priv->model = MV_MODEL_88X3310;
+		break;
+	case MARVELL_PHY_ID_88E2110:
+		if (nports == 8)
+			priv->model = MV_MODEL_88E218X;
+		else if (nports == 1)
+			priv->model = MV_MODEL_88E211X;
+		break;
+	default:
+		unreachable();
+	}
+
+	if (!priv->model) {
+		phydev_err(phydev, "unknown PHY model (nports = %i)\n", nports);
+		return -ENODEV;
+	}
+
 	/* Powering down the port when not in use saves about 600mW */
 	ret = mv3310_power_down(phydev);
 	if (ret)
-- 
2.26.2

[PATCH net-next v2 08/12] net: phy: marvell10g: support all rate matching modes

[Marek Behún]

Add support for all rate matching modes, not only for 10gbase-r.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 67 ++++++++++++++++++++++++++++++------
 1 file changed, 57 insertions(+), 10 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index b49cff895cdd..025473512581 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -124,6 +124,7 @@ struct mv3310_priv {
 	enum mv3310_model model;
 
 	u32 firmware_ver;
+	phy_interface_t const_interface;
 	bool rate_match;
 
 	struct device *hwmon_dev;
@@ -512,11 +513,56 @@ static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
 		MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
 }
 
-static int mv3310_config_init(struct phy_device *phydev)
+static int mv2110_init_interface(struct phy_device *phydev)
+{
+	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+	int mactype;
+
+	mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
+	if (mactype < 0)
+		return mactype;
+
+	mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
+
+	if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) {
+		priv->rate_match = true;
+		priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
+	}
+
+	return 0;
+}
+
+static int mv3310_init_interface(struct phy_device *phydev)
 {
 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+	int mactype;
+
+	mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
+	if (mactype < 0)
+		return mactype;
+
+	mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
+
+	if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
+	    mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
+	    (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH &&
+	     priv->model == MV_MODEL_88X3310))
+		priv->rate_match = true;
+
+	if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
+		priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
+	else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH)
+		priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
+	else if (priv->model == MV_MODEL_88X3310 &&
+		 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
+		priv->const_interface = PHY_INTERFACE_MODE_XAUI;
+
+	return 0;
+}
+
+static int mv3310_config_init(struct phy_device *phydev)
+{
 	int err;
-	int val;
 
 	/* Check that the PHY interface type is compatible */
 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
@@ -535,11 +581,12 @@ static int mv3310_config_init(struct phy_device *phydev)
 	if (err)
 		return err;
 
-	val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
-	if (val < 0)
-		return val;
-	priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
-			MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH);
+	if (phydev->drv->phy_id == MARVELL_PHY_ID_88E2110)
+		err = mv2110_init_interface(phydev);
+	else
+		err = mv3310_init_interface(phydev);
+	if (err < 0)
+		return err;
 
 	/* Enable EDPD mode - saving 600mW */
 	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
@@ -649,12 +696,12 @@ static void mv3310_update_interface(struct phy_device *phydev)
 {
 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
 
-	/* In "XFI with Rate Matching" mode the PHY interface is fixed at
-	 * 10Gb. The PHY adapts the rate to actual wire speed with help of
+	/* In all of the "* with Rate Matching" modes the PHY interface is fixed
+	 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
 	 * internal 16KB buffer.
 	 */
 	if (priv->rate_match) {
-		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+		phydev->interface = priv->const_interface;
 		return;
 	}
 
-- 
2.26.2

[PATCH net-next v2 09/12] net: phy: marvell10g: support other MACTYPEs

[Marek Behún]

Currently the only "changing" MACTYPE we support is when the PHY changes
between
  10gbase-r / 5gbase-r / 2500base-x / sgmii

Add support for
  xaui / 5gbase-r / 2500base-x / sgmii
  rxaui / 5gbase-r / 2500base-x / sgmii

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 95 +++++++++++++++++++++++-------------
 1 file changed, 60 insertions(+), 35 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 025473512581..6df67c12f012 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -524,10 +524,21 @@ static int mv2110_init_interface(struct phy_device *phydev)
 
 	mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
 
-	if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) {
+	if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
 		priv->rate_match = true;
+
+	if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII ||
+	    (priv->model == MV_MODEL_88E218X &&
+	     (mactype == MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII ||
+	      mactype == MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII)))
+		priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
+	else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
 		priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
-	}
+	else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
+		 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
+		priv->const_interface = PHY_INTERFACE_MODE_NA;
+	else
+		return -EINVAL;
 
 	return 0;
 }
@@ -549,13 +560,23 @@ static int mv3310_init_interface(struct phy_device *phydev)
 	     priv->model == MV_MODEL_88X3310))
 		priv->rate_match = true;
 
-	if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
+	if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
+		priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
+	else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
+		 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
+		 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
 		priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
-	else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH)
+	else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
+		 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI ||
+		 (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN &&
+		  priv->model == MV_MODEL_88X3340))
 		priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
 	else if (priv->model == MV_MODEL_88X3310 &&
-		 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
+		 (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
+		  mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI))
 		priv->const_interface = PHY_INTERFACE_MODE_XAUI;
+	else
+		return -EINVAL;
 
 	return 0;
 }
@@ -585,8 +606,10 @@ static int mv3310_config_init(struct phy_device *phydev)
 		err = mv2110_init_interface(phydev);
 	else
 		err = mv3310_init_interface(phydev);
-	if (err < 0)
+	if (err < 0) {
+		phydev_err(phydev, "MACTYPE configuration invalid\n");
 		return err;
+	}
 
 	/* Enable EDPD mode - saving 600mW */
 	return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
@@ -696,6 +719,9 @@ static void mv3310_update_interface(struct phy_device *phydev)
 {
 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
 
+	if (!phydev->link)
+		return;
+
 	/* In all of the "* with Rate Matching" modes the PHY interface is fixed
 	 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
 	 * internal 16KB buffer.
@@ -705,35 +731,34 @@ static void mv3310_update_interface(struct phy_device *phydev)
 		return;
 	}
 
-	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
-	     phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
-	     phydev->interface == PHY_INTERFACE_MODE_5GBASER ||
-	     phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
-	    phydev->link) {
-		/* The PHY automatically switches its serdes interface (and
-		 * active PHYXS instance) between Cisco SGMII, 10GBase-R and
-		 * 2500BaseX modes according to the speed.  Florian suggests
-		 * setting phydev->interface to communicate this to the MAC.
-		 * Only do this if we are already in one of the above modes.
-		 */
-		switch (phydev->speed) {
-		case SPEED_10000:
-			phydev->interface = PHY_INTERFACE_MODE_10GBASER;
-			break;
-		case SPEED_5000:
-			phydev->interface = PHY_INTERFACE_MODE_5GBASER;
-			break;
-		case SPEED_2500:
-			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-			break;
-		case SPEED_1000:
-		case SPEED_100:
-		case SPEED_10:
-			phydev->interface = PHY_INTERFACE_MODE_SGMII;
-			break;
-		default:
-			break;
-		}
+	if (priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
+		phydev->interface = PHY_INTERFACE_MODE_USXGMII;
+		return;
+	}
+
+	/* The PHY automatically switches its serdes interface (and active PHYXS
+	 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
+	 * xaui / rxaui modes according to the speed.
+	 * Florian suggests setting phydev->interface to communicate this to the
+	 * MAC. Only do this if we are already in one of the above modes.
+	 */
+	switch (phydev->speed) {
+	case SPEED_10000:
+		phydev->interface = priv->const_interface;
+		break;
+	case SPEED_5000:
+		phydev->interface = PHY_INTERFACE_MODE_5GBASER;
+		break;
+	case SPEED_2500:
+		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+		break;
+	case SPEED_1000:
+	case SPEED_100:
+	case SPEED_10:
+		phydev->interface = PHY_INTERFACE_MODE_SGMII;
+		break;
+	default:
+		break;
 	}
 }
 
-- 
2.26.2

[PATCH net-next v2 10/12] net: phy: add constants for 2.5G and 5G speed in PCS speed register

[Marek Behún]

Add constants for 2.5G and 5G speed in PCS speed register into mdio.h.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 include/uapi/linux/mdio.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index 3f302e2523b2..bdf77dffa5a4 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -120,6 +120,8 @@
 #define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
 #define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
 #define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */
+#define MDIO_PCS_SPEED_2_5G		0x0040	/* 2.5G capable */
+#define MDIO_PCS_SPEED_5G		0x0080	/* 5G capable */
 
 /* Device present registers. */
 #define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
-- 
2.26.2

[PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Marek Behún]

Print exact mode, one of
  88E2110
  88E2111
  88E2180
  88E2181
  88X3310
  88X3310P
  88X3340
  88X3340P

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 6df67c12f012..84f24fcb832c 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -33,6 +33,8 @@
 #define MV_PHY_ALASKA_NBT_QUIRK_REV	(MARVELL_PHY_ID_88X3310 | 0xa)
 
 enum {
+	MV_PMA_XGSTAT		= 0xc001,
+	MV_PMA_XGSTAT_NO_MACSEC	= BIT(12),
 	MV_PMA_FW_VER0		= 0xc011,
 	MV_PMA_FW_VER1		= 0xc012,
 	MV_PMA_21X0_PORT_CTRL	= 0xc04a,
@@ -397,6 +399,7 @@ static int mv3310_probe(struct phy_device *phydev)
 {
 	struct mv3310_priv *priv;
 	u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
+	bool has_5g, has_macsec;
 	int ret, nports;
 
 	if (!phydev->is_c45 ||
@@ -443,12 +446,24 @@ static int mv3310_probe(struct phy_device *phydev)
 
 	switch (phydev->drv->phy_id) {
 	case MARVELL_PHY_ID_88X3310:
+		ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_XGSTAT);
+		if (ret < 0)
+			return ret;
+
+		has_macsec = !(ret & MV_PMA_XGSTAT_NO_MACSEC);
+
 		if (nports == 4)
 			priv->model = MV_MODEL_88X3340;
 		else if (nports == 1)
 			priv->model = MV_MODEL_88X3310;
 		break;
 	case MARVELL_PHY_ID_88E2110:
+		ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
+		if (ret < 0)
+			return ret;
+
+		has_5g = ret & MDIO_PCS_SPEED_5G;
+
 		if (nports == 8)
 			priv->model = MV_MODEL_88E218X;
 		else if (nports == 1)
@@ -458,7 +473,17 @@ static int mv3310_probe(struct phy_device *phydev)
 		unreachable();
 	}
 
-	if (!priv->model) {
+	switch (priv->model) {
+	case MV_MODEL_88E211X:
+	case MV_MODEL_88E218X:
+		phydev_info(phydev, "model 88E21%d%d\n", nports, !has_5g);
+		break;
+	case MV_MODEL_88X3310:
+	case MV_MODEL_88X3340:
+		phydev_info(phydev, "model 88X33%d0%s\n", nports,
+			    has_macsec ? "P" : "");
+		break;
+	default:
 		phydev_err(phydev, "unknown PHY model (nports = %i)\n", nports);
 		return -ENODEV;
 	}
-- 
2.26.2

[PATCH net-next v2 12/12] net: phy: marvell10g: better check for compatible interface

[Marek Behún]

Do a model-specific check for compatible interface:
- 88X3340 does not support XAUI
- 88E21XX does not support XAUI and RXAUI
- 88E21X1 does not support 5gbase-r

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/marvell10g.c | 38 ++++++++++++++++++++++++------------
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 84f24fcb832c..510e27c766e6 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -124,6 +124,7 @@ enum mv3310_model {
 
 struct mv3310_priv {
 	enum mv3310_model model;
+	bool has_5g;
 
 	u32 firmware_ver;
 	phy_interface_t const_interface;
@@ -399,7 +400,7 @@ static int mv3310_probe(struct phy_device *phydev)
 {
 	struct mv3310_priv *priv;
 	u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
-	bool has_5g, has_macsec;
+	bool has_macsec;
 	int ret, nports;
 
 	if (!phydev->is_c45 ||
@@ -451,6 +452,7 @@ static int mv3310_probe(struct phy_device *phydev)
 			return ret;
 
 		has_macsec = !(ret & MV_PMA_XGSTAT_NO_MACSEC);
+		priv->has_5g = true;
 
 		if (nports == 4)
 			priv->model = MV_MODEL_88X3340;
@@ -462,7 +464,7 @@ static int mv3310_probe(struct phy_device *phydev)
 		if (ret < 0)
 			return ret;
 
-		has_5g = ret & MDIO_PCS_SPEED_5G;
+		priv->has_5g = ret & MDIO_PCS_SPEED_5G;
 
 		if (nports == 8)
 			priv->model = MV_MODEL_88E218X;
@@ -476,7 +478,7 @@ static int mv3310_probe(struct phy_device *phydev)
 	switch (priv->model) {
 	case MV_MODEL_88E211X:
 	case MV_MODEL_88E218X:
-		phydev_info(phydev, "model 88E21%d%d\n", nports, !has_5g);
+		phydev_info(phydev, "model 88E21%d%d\n", nports, !priv->has_5g);
 		break;
 	case MV_MODEL_88X3310:
 	case MV_MODEL_88X3340:
@@ -543,6 +545,15 @@ static int mv2110_init_interface(struct phy_device *phydev)
 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
 	int mactype;
 
+	/* Check that the PHY interface type is compatible */
+	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+	    (phydev->interface != PHY_INTERFACE_MODE_5GBASER ||
+	     !priv->has_5g) &&
+	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
+	    phydev->interface != PHY_INTERFACE_MODE_USXGMII)
+		return -ENODEV;
+
 	mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
 	if (mactype < 0)
 		return mactype;
@@ -573,6 +584,17 @@ static int mv3310_init_interface(struct phy_device *phydev)
 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
 	int mactype;
 
+	/* Check that the PHY interface type is compatible */
+	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+	    phydev->interface != PHY_INTERFACE_MODE_5GBASER &&
+	    (phydev->interface != PHY_INTERFACE_MODE_XAUI ||
+	     priv->model == MV_MODEL_88X3340) &&
+	    phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
+	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
+	    phydev->interface != PHY_INTERFACE_MODE_USXGMII)
+		return -ENODEV;
+
 	mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
 	if (mactype < 0)
 		return mactype;
@@ -610,16 +632,6 @@ static int mv3310_config_init(struct phy_device *phydev)
 {
 	int err;
 
-	/* Check that the PHY interface type is compatible */
-	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
-	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
-	    phydev->interface != PHY_INTERFACE_MODE_5GBASER &&
-	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
-	    phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
-	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
-	    phydev->interface != PHY_INTERFACE_MODE_USXGMII)
-		return -ENODEV;
-
 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 
 	/* Power up so reset works */
-- 
2.26.2

Re: [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Marek Behún]

On Thu, 25 Mar 2021 14:12:49 +0100
Marek Behún <kabel@kernel.org> wrote:

> Print exact mode, one of

typo: model

Re: [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Russell King - ARM Linux admin]

On Thu, Mar 25, 2021 at 02:12:49PM +0100, Marek Behún wrote:
> @@ -443,12 +446,24 @@ static int mv3310_probe(struct phy_device *phydev)
>  
>  	switch (phydev->drv->phy_id) {
>  	case MARVELL_PHY_ID_88X3310:
> +		ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_XGSTAT);
> +		if (ret < 0)
> +			return ret;
> +
> +		has_macsec = !(ret & MV_PMA_XGSTAT_NO_MACSEC);
> +
>  		if (nports == 4)
>  			priv->model = MV_MODEL_88X3340;
>  		else if (nports == 1)
>  			priv->model = MV_MODEL_88X3310;
>  		break;

The 88X3310 and 88X3340 can be differentiated by bit 3 in the revision.
In other words, 88X3310 is 0x09a0..0x09a7, and 88X3340 is
0x09a8..0x09af. We could add a separate driver structure, which would
then allow the kernel to print a more specific string via standard
methods, like we do for other PHYs. Not sure whether that would work
for the 88X21x0 family though.
-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Marek Behún]

On Thu, 25 Mar 2021 15:54:52 +0000
Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:

> On Thu, Mar 25, 2021 at 02:12:49PM +0100, Marek Behún wrote:
> > @@ -443,12 +446,24 @@ static int mv3310_probe(struct phy_device *phydev)
> >  
> >  	switch (phydev->drv->phy_id) {
> >  	case MARVELL_PHY_ID_88X3310:
> > +		ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_XGSTAT);
> > +		if (ret < 0)
> > +			return ret;
> > +
> > +		has_macsec = !(ret & MV_PMA_XGSTAT_NO_MACSEC);
> > +
> >  		if (nports == 4)
> >  			priv->model = MV_MODEL_88X3340;
> >  		else if (nports == 1)
> >  			priv->model = MV_MODEL_88X3310;
> >  		break;  
> 
> The 88X3310 and 88X3340 can be differentiated by bit 3 in the revision.
> In other words, 88X3310 is 0x09a0..0x09a7, and 88X3340 is
> 0x09a8..0x09af. We could add a separate driver structure, which would
> then allow the kernel to print a more specific string via standard
> methods, like we do for other PHYs. Not sure whether that would work
> for the 88X21x0 family though.

OK I will look into this. What are your thoughts on the other patches?

Marek

Re: [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Marek Behún]

On Thu, 25 Mar 2021 15:54:52 +0000
Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:

> The 88X3310 and 88X3340 can be differentiated by bit 3 in the revision.
> In other words, 88X3310 is 0x09a0..0x09a7, and 88X3340 is
> 0x09a8..0x09af. We could add a separate driver structure, which would
> then allow the kernel to print a more specific string via standard
> methods, like we do for other PHYs. Not sure whether that would work
> for the 88X21x0 family though.

According to release notes it seems that we can also differentiate
88E211X from 88E218X (via bit 3 in register 1.3):
 88E211X has 0x09B9
 88E218X has 0x09B1

but not 88E2110 from 88E2111
    nor 88E2180 from 88E2181.

These can be differentiated via register
  3.0004.7
(bit 7 of MDIO_MMD_PCS.MDIO_SPEED., which says whether device is capable
 of 5g speed)

I propose creating separate structures for mv88x3340 and mv88e218x.
We can then print the remaining info as
  "(not) macsec/ptp capable"
or
  "(not) 5g capable"

What do you think?

Marek

Re: [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Heiner Kallweit]

On 25.03.2021 21:29, Marek Behún wrote:
> On Thu, 25 Mar 2021 15:54:52 +0000
> Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:
> 
>> The 88X3310 and 88X3340 can be differentiated by bit 3 in the revision.
>> In other words, 88X3310 is 0x09a0..0x09a7, and 88X3340 is
>> 0x09a8..0x09af. We could add a separate driver structure, which would
>> then allow the kernel to print a more specific string via standard
>> methods, like we do for other PHYs. Not sure whether that would work
>> for the 88X21x0 family though.
> 
> According to release notes it seems that we can also differentiate
> 88E211X from 88E218X (via bit 3 in register 1.3):
>  88E211X has 0x09B9
>  88E218X has 0x09B1
> 
> but not 88E2110 from 88E2111
>     nor 88E2180 from 88E2181.
> 
> These can be differentiated via register
>   3.0004.7
> (bit 7 of MDIO_MMD_PCS.MDIO_SPEED., which says whether device is capable
>  of 5g speed)
> 

If the PHY ID's are the same but you can use this register to
differentiate the two versions, then you could implement the
match_phy_device callback. This would allow you to have separate
PHY drivers. This is just meant to say you have this option, I don't
know the context good enough to state whether it's the better one.


> I propose creating separate structures for mv88x3340 and mv88e218x.
> We can then print the remaining info as
>   "(not) macsec/ptp capable"
> or
>   "(not) 5g capable"
> 
> What do you think?
> 
> Marek
> 

Re: [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Marek Behún]

On Thu, 25 Mar 2021 21:44:21 +0100
Heiner Kallweit <hkallweit1@gmail.com> wrote:

> On 25.03.2021 21:29, Marek Behún wrote:
> > On Thu, 25 Mar 2021 15:54:52 +0000
> > Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:
> >   
> >> The 88X3310 and 88X3340 can be differentiated by bit 3 in the revision.
> >> In other words, 88X3310 is 0x09a0..0x09a7, and 88X3340 is
> >> 0x09a8..0x09af. We could add a separate driver structure, which would
> >> then allow the kernel to print a more specific string via standard
> >> methods, like we do for other PHYs. Not sure whether that would work
> >> for the 88X21x0 family though.  
> > 
> > According to release notes it seems that we can also differentiate
> > 88E211X from 88E218X (via bit 3 in register 1.3):
> >  88E211X has 0x09B9
> >  88E218X has 0x09B1
> > 
> > but not 88E2110 from 88E2111
> >     nor 88E2180 from 88E2181.
> > 
> > These can be differentiated via register
> >   3.0004.7
> > (bit 7 of MDIO_MMD_PCS.MDIO_SPEED., which says whether device is capable
> >  of 5g speed)
> >   
> 
> If the PHY ID's are the same but you can use this register to
> differentiate the two versions, then you could implement the
> match_phy_device callback. This would allow you to have separate
> PHY drivers. This is just meant to say you have this option, I don't
> know the context good enough to state whether it's the better one.

Nice, didn't know about that. But I fear whether this would always work
for the 88X3310 vs 88X3310P, it is possible that this feature is only
recognizable if the firmware in the PHY is already running.

I shall look into this.

Marek

Re: [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Russell King - ARM Linux admin]

On Thu, Mar 25, 2021 at 09:54:14PM +0100, Marek Behún wrote:
> On Thu, 25 Mar 2021 21:44:21 +0100
> Heiner Kallweit <hkallweit1@gmail.com> wrote:
> 
> > On 25.03.2021 21:29, Marek Behún wrote:
> > > On Thu, 25 Mar 2021 15:54:52 +0000
> > > Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:
> > >   
> > >> The 88X3310 and 88X3340 can be differentiated by bit 3 in the revision.
> > >> In other words, 88X3310 is 0x09a0..0x09a7, and 88X3340 is
> > >> 0x09a8..0x09af. We could add a separate driver structure, which would
> > >> then allow the kernel to print a more specific string via standard
> > >> methods, like we do for other PHYs. Not sure whether that would work
> > >> for the 88X21x0 family though.  
> > > 
> > > According to release notes it seems that we can also differentiate
> > > 88E211X from 88E218X (via bit 3 in register 1.3):
> > >  88E211X has 0x09B9
> > >  88E218X has 0x09B1
> > > 
> > > but not 88E2110 from 88E2111
> > >     nor 88E2180 from 88E2181.
> > > 
> > > These can be differentiated via register
> > >   3.0004.7
> > > (bit 7 of MDIO_MMD_PCS.MDIO_SPEED., which says whether device is capable
> > >  of 5g speed)
> > >   
> > 
> > If the PHY ID's are the same but you can use this register to
> > differentiate the two versions, then you could implement the
> > match_phy_device callback. This would allow you to have separate
> > PHY drivers. This is just meant to say you have this option, I don't
> > know the context good enough to state whether it's the better one.
> 
> Nice, didn't know about that. But I fear whether this would always work
> for the 88X3310 vs 88X3310P, it is possible that this feature is only
> recognizable if the firmware in the PHY is already running.

The ID registers aren't programmable and contain the proper IDs even if
there isn't firmware loaded (I've had such a PHY here.)

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Re: [PATCH net-next v2 11/12] net: phy: marvell10g: print exact model

[Marek Behún]

On Fri, 26 Mar 2021 09:07:34 +0000
Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:

> > Nice, didn't know about that. But I fear whether this would always work
> > for the 88X3310 vs 88X3310P, it is possible that this feature is only
> > recognizable if the firmware in the PHY is already running.  
> 
> The ID registers aren't programmable and contain the proper IDs even if
> there isn't firmware loaded (I've had such a PHY here.)
> 

Yes, but the macsec feature bit is in register
MDIO_MMD_PMAPMD.MV_PMA_XGSTAT.12 (1.c001.12)

But it says "This bit is valid upon completion of reset (1.0.15 = 0)",
so it seems we can use this. :)

Marek