From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Ling Pei Lee <pei.lee.ling@intel.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
davem@davemloft.net, Jakub Kicinski <kuba@kernel.org>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
Marek Behun <marek.behun@nic.cz>,
weifeng.voon@intel.com, vee.khee.wong@linux.intel.com,
vee.khee.wong@intel.com
Subject: Re: [PATCH net-next] net: phy: marvell10g: enable WoL for mv2110
Date: Thu, 24 Jun 2021 16:34:28 +0100 [thread overview]
Message-ID: <20210624153428.GR22278@shell.armlinux.org.uk> (raw)
In-Reply-To: <20210623130929.805559-1-pei.lee.ling@intel.com>
On Wed, Jun 23, 2021 at 09:09:29PM +0800, Ling Pei Lee wrote:
> @@ -106,6 +107,17 @@ enum {
> MV_V2_TEMP_CTRL_DISABLE = 0xc000,
> MV_V2_TEMP = 0xf08c,
> MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
> + MV_V2_MAGIC_PKT_WORD0 = 0xf06b,
> + MV_V2_MAGIC_PKT_WORD1 = 0xf06c,
> + MV_V2_MAGIC_PKT_WORD2 = 0xf06d,
> + /* Wake on LAN registers */
> + MV_V2_WOL_CTRL = 0xf06e,
> + MV_V2_WOL_STS = 0xf06f,
> + MV_V2_WOL_CLEAR_STS = BIT(15),
> + MV_V2_WOL_MAGIC_PKT_EN = BIT(0),
> + MV_V2_PORT_INTR_STS = 0xf040,
> + MV_V2_PORT_INTR_MASK = 0xf043,
> + MV_V2_WOL_INTR_EN = BIT(8),
Please put these new register definitions in address order. This list is
first sorted by MMD and then by address. So these should be before the
definition of MV_V2_TEMP_CTRL.
As I suspected, the 88x3310 shares this same register layout for the WOL
and at least bit 8 of the interrupt status and enable registers.
Thanks, and thanks for reminding me to look at this today!
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
prev parent reply other threads:[~2021-06-24 15:34 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-23 13:09 [PATCH net-next] net: phy: marvell10g: enable WoL for mv2110 Ling Pei Lee
2021-06-23 20:06 ` Russell King (Oracle)
2021-06-24 15:27 ` Wong Vee Khee
2021-06-23 21:38 ` Marek Behun
2021-06-24 2:56 ` Wong Vee Khee
2021-06-24 15:34 ` Russell King (Oracle) [this message]
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