netdev.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Ansuel Smith <ansuelsmth@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>,
	Vivien Didelot <vivien.didelot@gmail.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Vladimir Oltean <olteanv@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Russell King <linux@armlinux.org.uk>,
	netdev@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Ansuel Smith <ansuelsmth@gmail.com>
Subject: [net-next PATCH v5 10/14] drivers: net: dsa: qca8k: add support for pws config reg
Date: Mon, 11 Oct 2021 03:30:20 +0200	[thread overview]
Message-ID: <20211011013024.569-11-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20211011013024.569-1-ansuelsmth@gmail.com>

Some qca8327 switch require to force the ignore of power on sel
strapping. Some switch require to set the led open drain mode in regs
instead of using strapping. While most of the device implements this
using the correct way using pin strapping, there are still some broken
device that require to be set using sw regs.
Introduce a new binding and support these special configuration.
As led open drain require to ignore pin strapping to work, the probe
fails with EINVAL error with incorrect configuration.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 39 +++++++++++++++++++++++++++++++++++++++
 drivers/net/dsa/qca8k.h |  6 ++++++
 2 files changed, 45 insertions(+)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index c5aee1aee550..e9c16f82a373 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -931,6 +931,41 @@ static int qca8k_find_cpu_port(struct dsa_switch *ds)
 	return -EINVAL;
 }
 
+static int
+qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
+{
+	struct device_node *node = priv->dev->of_node;
+	u32 val = 0;
+	int ret;
+
+	/* QCA8327 require to set to the correct mode.
+	 * His bigger brother QCA8328 have the 172 pin layout.
+	 * Should be applied by default but we set this just to make sure.
+	 */
+	if (priv->switch_id == QCA8K_ID_QCA8327) {
+		ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
+				QCA8327_PWS_PACKAGE148_EN);
+		if (ret)
+			return ret;
+	}
+
+	if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
+		val |= QCA8K_PWS_POWER_ON_SEL;
+
+	if (of_property_read_bool(node, "qca,led-open-drain")) {
+		if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
+			dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
+			return -EINVAL;
+		}
+
+		val |= QCA8K_PWS_LED_OPEN_EN_CSR;
+	}
+
+	return qca8k_rmw(priv, QCA8K_REG_PWS,
+			QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
+			val);
+}
+
 static int
 qca8k_parse_port_config(struct qca8k_priv *priv)
 {
@@ -1047,6 +1082,10 @@ qca8k_setup(struct dsa_switch *ds)
 	if (ret)
 		return ret;
 
+	ret = qca8k_setup_of_pws_reg(priv);
+	if (ret)
+		return ret;
+
 	ret = qca8k_setup_mac_pwr_sel(priv);
 	if (ret)
 		return ret;
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 77b1677edafa..35a471bfd27f 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -46,6 +46,12 @@
 #define   QCA8K_MAX_DELAY				3
 #define   QCA8K_PORT_PAD_SGMII_EN			BIT(7)
 #define QCA8K_REG_PWS					0x010
+#define   QCA8K_PWS_POWER_ON_SEL			BIT(31)
+/* This reg is only valid for QCA832x and toggle the package
+ * type from 176 pin (by default) to 148 pin used on QCA8327
+ */
+#define   QCA8327_PWS_PACKAGE148_EN			BIT(30)
+#define   QCA8K_PWS_LED_OPEN_EN_CSR			BIT(24)
 #define   QCA8K_PWS_SERDES_AEN_DIS			BIT(7)
 #define QCA8K_REG_MODULE_EN				0x030
 #define   QCA8K_MODULE_EN_MIB				BIT(0)
-- 
2.32.0


  parent reply	other threads:[~2021-10-11  1:31 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-11  1:30 [net-next PATCH v5 00/14] Multiple improvement for qca8337 switch Ansuel Smith
2021-10-11  1:30 ` [net-next PATCH v5 01/14] net: dsa: qca8k: add mac_power_sel support Ansuel Smith
2021-10-11  1:47   ` Florian Fainelli
2021-10-11  1:30 ` [net-next PATCH v5 02/14] dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties Ansuel Smith
2021-10-11  1:48   ` Florian Fainelli
2021-10-11  1:30 ` [net-next PATCH v5 03/14] net: dsa: qca8k: add support for sgmii falling edge Ansuel Smith
2021-10-11  1:49   ` Florian Fainelli
2021-10-11  1:30 ` [net-next PATCH v5 04/14] dt-bindings: net: dsa: qca8k: Document support for CPU port 6 Ansuel Smith
2021-10-11  1:50   ` Florian Fainelli
2021-10-11  2:02     ` Ansuel Smith
2021-10-11  1:30 ` [net-next PATCH v5 05/14] drivers: net: dsa: qca8k: add support for cpu " Ansuel Smith
2021-10-11  2:01   ` Florian Fainelli
2021-10-11  4:49   ` DENG Qingfang
2021-10-11  1:30 ` [net-next PATCH v5 06/14] net: dsa: qca8k: rework rgmii delay logic and scan " Ansuel Smith
2021-10-11  2:11   ` Florian Fainelli
2021-10-11  2:45   ` Florian Fainelli
2021-10-11  5:15   ` kernel test robot
2021-10-11  1:30 ` [net-next PATCH v5 07/14] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Ansuel Smith
2021-10-11  1:30 ` [net-next PATCH v5 08/14] net: dsa: qca8k: add explicit SGMII PLL enable Ansuel Smith
2021-10-11  2:46   ` Florian Fainelli
2021-10-11  1:30 ` [net-next PATCH v5 09/14] dt-bindings: net: dsa: qca8k: Document qca,led-open-drain binding Ansuel Smith
2021-10-11  1:30 ` Ansuel Smith [this message]
2021-10-11  2:48   ` [net-next PATCH v5 10/14] drivers: net: dsa: qca8k: add support for pws config reg Florian Fainelli
2021-10-11  1:30 ` [net-next PATCH v5 11/14] dt-bindings: net: dsa: qca8k: document support for qca8328 Ansuel Smith
2021-10-11  1:58   ` Florian Fainelli
2021-10-11  1:30 ` [net-next PATCH v5 12/14] drivers: net: dsa: qca8k: add support for QCA8328 Ansuel Smith
2021-10-11  2:42   ` Florian Fainelli
2021-10-11  1:30 ` [net-next PATCH v5 13/14] drivers: net: dsa: qca8k: set internal delay also for sgmii Ansuel Smith
2021-10-11  2:44   ` Florian Fainelli
2021-10-11  1:30 ` [net-next PATCH v5 14/14] drivers: net: dsa: qca8k: move port config to dedicated struct Ansuel Smith
2021-10-11  2:47   ` Florian Fainelli

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211011013024.569-11-ansuelsmth@gmail.com \
    --to=ansuelsmth@gmail.com \
    --cc=andrew@lunn.ch \
    --cc=davem@davemloft.net \
    --cc=devicetree@vger.kernel.org \
    --cc=f.fainelli@gmail.com \
    --cc=kuba@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux@armlinux.org.uk \
    --cc=netdev@vger.kernel.org \
    --cc=olteanv@gmail.com \
    --cc=robh+dt@kernel.org \
    --cc=vivien.didelot@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).