From: Saeed Mahameed <saeed@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>
Cc: netdev@vger.kernel.org, Shay Drory <shayd@nvidia.com>,
Moshe Shemesh <moshe@nvidia.com>, Parav Pandit <parav@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>
Subject: [net-next 11/14] net/mlx5: Let user configure event_eq_size param
Date: Mon, 25 Oct 2021 13:54:28 -0700 [thread overview]
Message-ID: <20211025205431.365080-12-saeed@kernel.org> (raw)
In-Reply-To: <20211025205431.365080-1-saeed@kernel.org>
From: Shay Drory <shayd@nvidia.com>
Event EQ is an EQ which received the notification of almost all the
events generated by the NIC.
Currently, each event EQ is taking 512KB of memory. This size is not
needed in most use cases, and is critical with large scale. Hence,
allow user to configure the size of the event EQ.
For example to reduce event EQ size to 64, execute::
$ devlink resource set pci/0000:00:0b.0 path /event_eq_size/ size 64
$ devlink dev reload pci/0000:00:0b.0
Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
Documentation/networking/devlink/mlx5.rst | 4 +++
.../net/ethernet/mellanox/mlx5/core/devlink.h | 1 +
.../ethernet/mellanox/mlx5/core/devlink_res.c | 26 ++++++++++++++++++-
drivers/net/ethernet/mellanox/mlx5/core/eq.c | 2 +-
include/linux/mlx5/eq.h | 1 -
5 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/Documentation/networking/devlink/mlx5.rst b/Documentation/networking/devlink/mlx5.rst
index 4e6020570292..5b77863f9c88 100644
--- a/Documentation/networking/devlink/mlx5.rst
+++ b/Documentation/networking/devlink/mlx5.rst
@@ -57,6 +57,10 @@ Resources
* - ``comp_eq_size``
- Control the size of I/O completion EQs.
* The default value is 1024, and the range is between 64 and 4096.
+ * - ``event_eq_size``
+ - Control the size of the asynchronous control events EQ.
+ * The default value is 4096, and the range is between 64 and 4096.
+
Info versions
=============
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.h b/drivers/net/ethernet/mellanox/mlx5/core/devlink.h
index 4192f23b1446..674415fd0b3a 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.h
@@ -8,6 +8,7 @@
enum mlx5_devlink_resource_id {
MLX5_DL_RES_COMP_EQ = 1,
+ MLX5_DL_RES_ASYNC_EQ,
__MLX5_ID_RES_MAX,
MLX5_ID_RES_MAX = __MLX5_ID_RES_MAX - 1,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink_res.c b/drivers/net/ethernet/mellanox/mlx5/core/devlink_res.c
index 3beedfb8534a..549d23745942 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/devlink_res.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink_res.c
@@ -7,6 +7,7 @@
enum {
MLX5_EQ_MIN_SIZE = 64,
MLX5_EQ_MAX_SIZE = 4096,
+ MLX5_NUM_ASYNC_EQE = 4096,
MLX5_COMP_EQ_SIZE = 1024,
};
@@ -23,13 +24,35 @@ static int comp_eq_res_register(struct mlx5_core_dev *dev)
&comp_eq_size);
}
+static int async_eq_resource_register(struct mlx5_core_dev *dev)
+{
+ struct devlink_resource_size_params async_eq_size;
+ struct devlink *devlink = priv_to_devlink(dev);
+
+ devlink_resource_size_params_init(&async_eq_size, MLX5_EQ_MIN_SIZE,
+ MLX5_EQ_MAX_SIZE, 1, DEVLINK_RESOURCE_UNIT_ENTRY);
+ return devlink_resource_register(devlink, "event_eq_size",
+ MLX5_NUM_ASYNC_EQE, MLX5_DL_RES_ASYNC_EQ,
+ DEVLINK_RESOURCE_ID_PARENT_TOP,
+ &async_eq_size);
+}
+
void mlx5_devlink_res_register(struct mlx5_core_dev *dev)
{
int err;
err = comp_eq_res_register(dev);
if (err)
- mlx5_core_err(dev, "Failed to register resources, err = %d\n", err);
+ goto err_msg;
+
+ err = async_eq_resource_register(dev);
+ if (err)
+ goto err;
+ return;
+err:
+ devlink_resources_unregister(priv_to_devlink(dev), NULL);
+err_msg:
+ mlx5_core_err(dev, "Failed to register resources, err = %d\n", err);
}
void mlx5_devlink_res_unregister(struct mlx5_core_dev *dev)
@@ -39,6 +62,7 @@ void mlx5_devlink_res_unregister(struct mlx5_core_dev *dev)
static const size_t default_vals[MLX5_ID_RES_MAX + 1] = {
[MLX5_DL_RES_COMP_EQ] = MLX5_COMP_EQ_SIZE,
+ [MLX5_DL_RES_ASYNC_EQ] = MLX5_NUM_ASYNC_EQE,
};
size_t mlx5_devlink_res_size(struct mlx5_core_dev *dev, enum mlx5_devlink_resource_id id)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
index 4dda6e2a4cbc..31e69067284b 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
@@ -647,7 +647,7 @@ static int create_async_eqs(struct mlx5_core_dev *dev)
param = (struct mlx5_eq_param) {
.irq_index = MLX5_IRQ_EQ_CTRL,
- .nent = MLX5_NUM_ASYNC_EQE,
+ .nent = mlx5_devlink_res_size(dev, MLX5_DL_RES_ASYNC_EQ),
};
gather_async_events_mask(dev, param.mask);
diff --git a/include/linux/mlx5/eq.h b/include/linux/mlx5/eq.h
index ea3ff5a8ced3..11161e427608 100644
--- a/include/linux/mlx5/eq.h
+++ b/include/linux/mlx5/eq.h
@@ -5,7 +5,6 @@
#define MLX5_CORE_EQ_H
#define MLX5_NUM_CMD_EQE (32)
-#define MLX5_NUM_ASYNC_EQE (0x1000)
#define MLX5_NUM_SPARE_EQE (0x80)
struct mlx5_eq;
--
2.31.1
next prev parent reply other threads:[~2021-10-25 20:54 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 20:54 [pull request][net-next 00/14] mlx5 updates 2021-10-25 Saeed Mahameed
2021-10-25 20:54 ` [net-next 01/14] net/mlx5e: don't write directly to netdev->dev_addr Saeed Mahameed
2021-10-26 12:30 ` patchwork-bot+netdevbpf
2021-10-25 20:54 ` [net-next 02/14] net/mlx5: Remove unnecessary checks for slow path flag Saeed Mahameed
2021-10-25 20:54 ` [net-next 03/14] net/mlx5: Fix unused function warning of mlx5i_flow_type_mask Saeed Mahameed
2021-10-25 20:54 ` [net-next 04/14] net/mlx5: Reduce flow counters bulk query buffer size for SFs Saeed Mahameed
2021-10-25 20:54 ` [net-next 05/14] net/mlx5: Extend health buffer dump Saeed Mahameed
2021-10-25 20:54 ` [net-next 06/14] net/mlx5: Print health buffer by log level Saeed Mahameed
2021-10-25 20:54 ` [net-next 07/14] net/mlx5: Add periodic update of host time to firmware Saeed Mahameed
2021-10-25 20:54 ` [net-next 08/14] net/mlx5: Bridge, extract code to lookup and del/notify entry Saeed Mahameed
2021-10-25 20:54 ` [net-next 09/14] net/mlx5: Bridge, support replacing existing FDB entry Saeed Mahameed
2021-10-25 20:54 ` [net-next 10/14] net/mlx5: Let user configure io_eq_size param Saeed Mahameed
2021-10-26 15:05 ` Jakub Kicinski
2021-10-26 15:54 ` Saeed Mahameed
2021-10-26 17:16 ` Jakub Kicinski
2021-10-26 18:01 ` Saeed Mahameed
2021-10-27 6:16 ` Gal Pressman
2021-10-25 20:54 ` Saeed Mahameed [this message]
2021-10-25 20:54 ` [net-next 12/14] net/mlx5: Let user configure max_macs param Saeed Mahameed
2021-10-25 20:54 ` [net-next 13/14] net/mlx5: SF, Add SF trace points Saeed Mahameed
2021-10-25 20:54 ` [net-next 14/14] net/mlx5: SF_DEV Add SF device " Saeed Mahameed
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