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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?pxItyU5Vvc/Owseq68cLqNXClxjPp6EvuAdAO6oUW2nFa0RQ+e6QrL0dGtub?= =?us-ascii?Q?22cTdyjOk2TNKotjHOg4Xq5NeJEpA/+qmsT/zpJTxZ8dYWNEENZGndIms+Fg?= =?us-ascii?Q?jdee9RGckTNBntl1JJoTVqzdx4qftSlG/frNFIWz6vMqlmfbYPqKXf2xt6Bh?= =?us-ascii?Q?n4Fl7DJJKNJ0lgzU6+971Xuu+6P7y1ox9QuJCLhJF/T31IaN8C9v+Yc+AFX/?= =?us-ascii?Q?Ku/WY/9K2JaywcxEtV0P/k6rM7CR8kPUDS1aOTGT6KBI7MtCdIbZB+UEZtwp?= =?us-ascii?Q?+Yibn4MZN4K2JHskuWaV/WavtGaZFfyJNg1H70iLbIEX7FktqBntb+VkZMP4?= =?us-ascii?Q?pUSgpVoOwTbQe9eV7gQgz67xMuTsZIx0M2bFYbDoOpaek0AmkMndOe7TwYJc?= =?us-ascii?Q?4L8e9wkmZRWel9NmcZSwRnymzcmKjOnDlpArbj987j2SV4CqAzqdWZbey2++?= =?us-ascii?Q?VJXghbxjOQpOaRcaTXpbAAkGnq4YgTnPX176qR2MGiYuqssySjkYw5TCWmVc?= =?us-ascii?Q?pjPFMArpSLb8h9VjH5MoQEFNG/qOap/HZb8ZqjvFnAUgfHmW/IY9KtxW6nRo?= =?us-ascii?Q?CejqpG9eRrMwhHYz2yV3xMUKeiGirGvcYtOfSXnL8uF1hjHknoNk2xkmmb7o?= =?us-ascii?Q?5yR80B0GErhbz9Dltuu7nna50EyJZr4ttN/YoZRiisVkkBmniLjkGWKNklVt?= =?us-ascii?Q?ywWHv+A9aAqcYJMjiLLRxbzzmxMSbh/g3MOhK/qz109KNVXPyXNzhdJrB2Zx?= =?us-ascii?Q?BH8YosWrRHm6Gi84MH4IXrEQxbpMLzhbkp2RtcReXcX4OLuJ8kIdLPEjJBFd?= =?us-ascii?Q?XF1aBQiWkuy8IVr546kffmQmBBEgsIijzzFmEJKryE3gAkUkzeAGWKs3jrW0?= =?us-ascii?Q?Qhc619j4T03dCNS1wrybvrjcisycUkr6dfusVAMOrJP7AdYg065Xq3OM3vIA?= =?us-ascii?Q?4gDqpIYew9VhAo2Loh+V5ZKoh4Roiji0MCOt0fWj7lYdZCu70IHfvMXNVC8/?= =?us-ascii?Q?/dWSxZ5ZN/gNrUkTVd6EealYBm1uz7IZuPrA4UHDkBy1VOlmDy4tS0M+WvFv?= =?us-ascii?Q?+Gi8kap1GBt6eDyiM0ljM7/etoyOZGHtzfmgwunnzUbaU1m3O5agvwak6eU0?= =?us-ascii?Q?+AbPqaiEKfuOTv4VpjC/fCL3xfFPbFV498KVz49pyzVwwWwAJ57tc7Dc2N6f?= =?us-ascii?Q?mtvQOkS10llseaJy/6/WKnv5iy4qUxRhksjcNOBle2C0QCe3KYcRiem5Hl+v?= =?us-ascii?Q?TxXOyeWzChsy/Hs/cHtIBIPuoANfZvX8y3/RU835zW1O8wfKi0LTkT8c9j3T?= =?us-ascii?Q?auxHZ9BvXZOyORyJ5hpXtXsW+ycDLveyYSmEUH0Em/vaaem4scvwIhQsUNTq?= =?us-ascii?Q?I7MJikhorRK2234yIftWAj3x5ocizJnPDptul1YtHIGBZducG3OdDOwRzZMw?= =?us-ascii?Q?GUqToeWJr4FDmvcpLAnlRb9OZNmHuoyfK9G+nbfWyUJwHJxYwwfNdCeAG46U?= =?us-ascii?Q?1r2xUt3Ix/7ePRnbUDENHAiWa99Lsw9dbPMU1IdD66uComfsW+5ydt2lvkQf?= =?us-ascii?Q?pKJ3HUmLBRWJzcSBfDdXnZHDl2ZPq7kB4KASHg6fR8kRRkLk2CVZI+F1Xbdk?= =?us-ascii?Q?672WrzP1BeTwAoivTLBrfAcxYU1EyxI+a5w9JXX588j88EWiO27PGg0givoS?= =?us-ascii?Q?pfXs2g=3D=3D?= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 35db09b5-94d8-46f4-dc37-08d9d0f9eda2 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2022 09:50:10.7255 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RUH2tHtGgcGC2FS9IoGOiTC6b/hCGZB0Bkb0tk4ApIQdeyteSLNjCyhvS70jNs7IctqV/wVYWOq7hnoYxYC4h7IsDapSH5Z2ldwdeHkICP4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR10MB5689 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Alexandre, Vladimir, and those with interest of Ocelot chips, I'm starting this thread to just touch base before I dive into any PCS changes for Ocelot. I've appreciated all your guidance, and the only time I felt I've been led astray is when Alexandre told me it should be easy :-) I'm at the point where I'm starting to integrate the additional 4 copper ports of the VSC7512 reference board. They are 4 ports connected through a QSGMII bus, to a VSC8514 phy. The 8514 driver seems to be getting invoked, and running just fine. Also, I was able to slightly modify (hack*) drivers/phy/mscc/phy-ocelot-serdes.c to work with my in-development ocelot-mfd. I believe that is what I need to configure the HSIO registers. (*the device_is_mfd info I was using falls apart with the HSIO/syscon/mfd implementation here, sadly. A new probe function would easily clean that up, but it is more for me to think about... I digress) I'm using these device tree settings: port@4 { reg = <4>; label = "swp4"; status = "okay"; phy-handle = <&sw_phy4>; phy-mode = "qsgmii"; phys = <&serdes 4 SERDES6G(0)>; }; port@5 { reg = <5>; label = "swp5"; status = "okay"; phy-handle = <&sw_phy5>; phy-mode = "qsgmii"; phys = <&serdes 5 SERDES6G(0)>; }; ... serdes: serdes { compatible = "mscc,vsc7514-serdes"; #phy-cells = <2>; }; mdio1: mdio1 { compatible = "mscc,ocelot-miim", pinctrl-names = "default"; pinctrl-0 = <&miim1>; #address-cells = <1>; #size-cells = <0>; sw_phy4: ethernet-phy@4 { reg = <0x4>; }; }; [ 3.886787] libphy: ocelot_ext MDIO bus: probed [ 5.345891] ocelot-ext-switch ocelot-ext-switch: PHY [ocelot-ext-switch-mii:00] driver [Generic PHY] (irq=POLL) [ 5.357341] ocelot-ext-switch ocelot-ext-switch: configuring for phy/internal link mode [ 5.372525] ocelot-ext-switch ocelot-ext-switch swp1 (uninitialized): PHY [ocelot-ext-switch-mii:01] driver [Generic PHY] (irq=POLL) [ 5.388865] ocelot-ext-switch ocelot-ext-switch swp2 (uninitialized): PHY [ocelot-ext-switch-mii:02] driver [Generic PHY] (irq=POLL) [ 5.405086] ocelot-ext-switch ocelot-ext-switch swp3 (uninitialized): PHY [ocelot-ext-switch-mii:03] driver [Generic PHY] (irq=POLL) [ 6.291876] ocelot-ext-switch ocelot-ext-switch swp4 (uninitialized): PHY [ocelot-miim1-mii:04] driver [Microsemi GE VSC8514 SyncE] (irq=POLL) [ 6.471891] ocelot-ext-switch ocelot-ext-switch swp5 (uninitialized): PHY [ocelot-miim1-mii:05] driver [Microsemi GE VSC8514 SyncE] (irq=POLL) [ 6.651895] ocelot-ext-switch ocelot-ext-switch swp6 (uninitialized): PHY [ocelot-miim1-mii:06] driver [Microsemi GE VSC8514 SyncE] (irq=POLL) [ 6.831879] ocelot-ext-switch ocelot-ext-switch swp7 (uninitialized): PHY [ocelot-miim1-mii:07] driver [Microsemi GE VSC8514 SyncE] (irq=POLL) It seems like that, along with everything in vsc7514_phylink_mac_config, should be everything I need for operation of the four ports through the 8512. I've added OCELOT_QUIRK_SGMII_PORTS_MUST_BE_UP - but I'm not sure that's a quirk I need. Plus the only behavior it currently adds is once the port is up, it never comes back down. The current behavior I'm seeing is links and rates get detected, packets appear to be getting transmitted (ethtool stats) but they aren't, and nothing is received on either end. Is there something I'm missing with the device tree? Or is this the purpose of the PCS driver I'm looking into? I'm getting a feeling that my configuration is correct, and that I need to add SerDes support for these ports in phylink_mac_config... I noticed that there's the "SGMII only for now" comment, and when I look at the reference application for the 7512 there's a comment "external phy uses QSGMII interface" that appears to set the SGMII_MODE_ENA bit to 0. Thank you as always for your time, Colin Foster.