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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?ywvmG9bwDsXXPX2tIbyjNu5fCIIzWsNUjZjqiSfPKY8PHl4zkZZcZpLovAiC?= =?us-ascii?Q?KY7APLsCewjOilBxnBNSPfOvWTpOHrsarndg62nV2L57/ypKoBAU6yt6s7Y9?= =?us-ascii?Q?Wtv3Py4qywqWc2+5dGMwg9a+5O5PpQFj4kCCyTgiPrM68HhiybK9UpXMMDdm?= =?us-ascii?Q?FGUDisQHtGYiI5MEXhZYR8lDAIDpFz6stl3d7Nbm0rYgL5+IPFDX/E4pTkfO?= =?us-ascii?Q?dNIdaFZ3e2PEOg0XaD56NWJ1jCv5rFtTVCUBDHEj5tek7X/sxQ21Kr7siPX6?= =?us-ascii?Q?mKxdZb26UcPT9uuPMBA1kpnkiMTlGcwvkic3ji0U3cnZvnpZDIw9FWksqgCs?= =?us-ascii?Q?7tw11mTyIW60SiknSz4Ri398dkVavUJ+14RnZRK4IOI0UHaFuQTwnf/XKTPL?= =?us-ascii?Q?1ZH9fb7OrZULvuyMobIVGfpX0ux5XhLrDmkixqpOG0b47LaI3pw7+FLnxdhC?= =?us-ascii?Q?5CnlhDVolPHEjt7SMUEMJjElO2uAvVeAqD0nw8m5mVROQKuq0mdeixAKlFJi?= =?us-ascii?Q?wKeElKmeFIr5U1vrl5OTzhkeZEECFQJOy54jjjIu4CI4qxA8fJoRpGDu/s/B?= =?us-ascii?Q?XjI8D7aQGgf7dGrCl3EQzEyPJm+zyq5shxEc2xQ26quJPTRp1Sv+cs41PGnN?= =?us-ascii?Q?pcVIbNVssw/Dol8hgTZaZaE+Vs0h2GEh/7BqLzhbZRi419GqyDGntonusTMw?= =?us-ascii?Q?jo4uayS+9/7wWI3G8iYTShx257fNexNyFi1hNhNgooZcbyLDYrLHgpojwnsK?= =?us-ascii?Q?Wcp+FIZoqQmvU1QunBumrZBe0gF/NtXgynvu2y9ixu46wsgp8zl73qwHS5Mg?= =?us-ascii?Q?ZH+iUPiDhf0g8kCAudh/zhdu0vduzanO4uhWqHXh2VnFAxEaeQrMLNDjH/iQ?= =?us-ascii?Q?lyH2LyfDRcsAJboJO9HWOVEMZQgzAdfU8QeYscZKApc1RnAesUNIw4Pknq+v?= =?us-ascii?Q?CNOjSTPCEUFzh+dnckodVPtFUcdBzkRbN2w62DcirgGphvYyXm9kiSfdLy50?= =?us-ascii?Q?wiK9Kql0yaH4xawAD5wpRTnCU7npDaWH22mrq3+8aPMZrMIBx8izdsPaiKzA?= =?us-ascii?Q?r7S4zuauoj5w3MNgRsP7f2s625dqqPaLHdw7ZAwuLGEYQ6S4rtfGZ7QLrmLD?= =?us-ascii?Q?rOojNHtmU5vIwlMS2EY1TSpoWgIr8h5BUH41/VCZsdQkPIuu1/XOc8uq17Nd?= =?us-ascii?Q?JUnqpUxFRP/nqd7ZxyfKY9bV4+aSkUT2u0Ub/owVMHr53tm5YFRO8O5Qy0hv?= =?us-ascii?Q?TEX2IhGNsMygbdYhoiorwslwll8sx78znZ30wewyitssnKsqObqCsecvEx8l?= =?us-ascii?Q?p8l/bRUVbCmSKvdfTFjRIbfLmE1rjUAvGfVbME7EYKRlpjEG2bXSNg8g/PtF?= =?us-ascii?Q?DRoNK5lBeZtA2TeyrJyKOxGpbl4WCPE0fGDa1ZgeYbGdEDy8KqWYzZ+ppW0p?= =?us-ascii?Q?azzER1lQ0uqgo7XHY9aA0j5sVyIQ/q6o7mu+ZnYVpISf4eYvP1o1Bdh9Ff6U?= =?us-ascii?Q?mTRBKGXNHaKh6UYEAh7PKGOI3o0bJCqoLigP+3Es2wbufMWDyJhvA7/rpgFp?= =?us-ascii?Q?4zuH1tq009mepihy01ux/8QWLo5wFul12YAA/HISr8KkfgpMvXw7UkKSLk8k?= =?us-ascii?Q?SuwX/9YWxG3ZUBiBYYMd102m6S/a3qdnbkrvWzNP8ON4AS+tHr/wDjWDfelY?= =?us-ascii?Q?LWjhsg=3D=3D?= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 757554a4-593f-4efa-b14e-08d9d13e5ae0 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2022 17:59:59.6394 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JilIPdMNPcP7cfZLr3FD7uH810d85N6jQLmab7lUijkSE5BTSibbGg3J69w4Jq4kNmY6rnNfgE3txVY5lwepdLCEXc9gK53EyI32xV3CPBo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR10MB4801 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Vladimir, On Thu, Jan 06, 2022 at 12:48:37PM +0200, Vladimir Oltean wrote: > Hi Colin, > > I'm sorry, but I have no direct experience with the SERDES and PCS of > the Ocelot switches, since those blocks were completely replaced from > the NXP instantiations I'm playing with. I realized that might be the case as I was writing this email. Thank you for still helping. > > On Thu, Jan 06, 2022 at 01:50:03AM -0800, Colin Foster wrote: > > Hi Alexandre, Vladimir, and those with interest of Ocelot chips, > > > > I'm starting this thread to just touch base before I dive into any PCS > > changes for Ocelot. I've appreciated all your guidance, and the only > > time I felt I've been led astray is when Alexandre told me it should be > > easy :-) > > > > I'm at the point where I'm starting to integrate the additional 4 copper > > ports of the VSC7512 reference board. They are 4 ports connected through > > a QSGMII bus, to a VSC8514 phy. > > > > The 8514 driver seems to be getting invoked, and running just fine. > > Also, I was able to slightly modify (hack*) > > drivers/phy/mscc/phy-ocelot-serdes.c to work with my in-development > > ocelot-mfd. I believe that is what I need to configure the HSIO > > registers. > > And are you also getting a reference to it and calling it, like the > ocelot driver does here? > > err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, phy_mode); > > Could we see that portion of the code in the felix driver? Oh, no I'm not. That's probably the hint that I need. I see that happens in VSC7514 probe before calling ocelot_port_init, unlike felix. Alright, there's some work for me to do! Thanks :) > > > > > (*the device_is_mfd info I was using falls apart with the > > HSIO/syscon/mfd implementation here, sadly. A new probe function would > > easily clean that up, but it is more for me to think about... I digress) > > > > I'm using these device tree settings: > > > > port@4 { > > reg = <4>; > > label = "swp4"; > > status = "okay"; > > phy-handle = <&sw_phy4>; > > phy-mode = "qsgmii"; > > phys = <&serdes 4 SERDES6G(0)>; > > }; > > port@5 { > > reg = <5>; > > label = "swp5"; > > status = "okay"; > > phy-handle = <&sw_phy5>; > > phy-mode = "qsgmii"; > > phys = <&serdes 5 SERDES6G(0)>; > > }; > > ... > > serdes: serdes { > > compatible = "mscc,vsc7514-serdes"; > > #phy-cells = <2>; > > }; > > mdio1: mdio1 { > > compatible = "mscc,ocelot-miim", > > pinctrl-names = "default"; > > pinctrl-0 = <&miim1>; > > #address-cells = <1>; > > #size-cells = <0>; > > > > sw_phy4: ethernet-phy@4 { > > reg = <0x4>; > > }; > > }; > > > > [ 3.886787] libphy: ocelot_ext MDIO bus: probed > > [ 5.345891] ocelot-ext-switch ocelot-ext-switch: PHY [ocelot-ext-switch-mii:00] driver [Generic PHY] (irq=POLL) > > [ 5.357341] ocelot-ext-switch ocelot-ext-switch: configuring for phy/internal link mode > > [ 5.372525] ocelot-ext-switch ocelot-ext-switch swp1 (uninitialized): PHY [ocelot-ext-switch-mii:01] driver [Generic PHY] (irq=POLL) > > [ 5.388865] ocelot-ext-switch ocelot-ext-switch swp2 (uninitialized): PHY [ocelot-ext-switch-mii:02] driver [Generic PHY] (irq=POLL) > > [ 5.405086] ocelot-ext-switch ocelot-ext-switch swp3 (uninitialized): PHY [ocelot-ext-switch-mii:03] driver [Generic PHY] (irq=POLL) > > [ 6.291876] ocelot-ext-switch ocelot-ext-switch swp4 (uninitialized): PHY [ocelot-miim1-mii:04] driver [Microsemi GE VSC8514 SyncE] (irq=POLL) > > [ 6.471891] ocelot-ext-switch ocelot-ext-switch swp5 (uninitialized): PHY [ocelot-miim1-mii:05] driver [Microsemi GE VSC8514 SyncE] (irq=POLL) > > [ 6.651895] ocelot-ext-switch ocelot-ext-switch swp6 (uninitialized): PHY [ocelot-miim1-mii:06] driver [Microsemi GE VSC8514 SyncE] (irq=POLL) > > [ 6.831879] ocelot-ext-switch ocelot-ext-switch swp7 (uninitialized): PHY [ocelot-miim1-mii:07] driver [Microsemi GE VSC8514 SyncE] (irq=POLL) > > > > > > It seems like that, along with everything in vsc7514_phylink_mac_config, > > should be everything I need for operation of the four ports through the > > 8512. I've added OCELOT_QUIRK_SGMII_PORTS_MUST_BE_UP - but I'm not sure > > that's a quirk I need. Plus the only behavior it currently adds is once > > the port is up, it never comes back down. > > Correct. I noticed that the code was structured to do this when I > converted it to phylink, but I don't know if it's needed either. I just > named that behavior as OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP and made it > optional. I'll report my findings. > > > The current behavior I'm seeing is links and rates get detected, packets > > appear to be getting transmitted (ethtool stats) but they aren't, and > > nothing is received on either end. > > could you also check ethtool --phy-statistics swp4 on both ends? phy_cu_media_link_disconnect increments as expected. No activity on phy_cu_media_crc_good_count. I feel like it probably isn't worth digging too much into this until I fix the phy_set_mode_ext. > > > Is there something I'm missing with the device tree? Or is this the > > purpose of the PCS driver I'm looking into? I'm getting a feeling that > > my configuration is correct, and that I need to add SerDes support for > > these ports in phylink_mac_config... I noticed that there's the "SGMII > > only for now" comment, and when I look at the reference application for > > the 7512 there's a comment "external phy uses QSGMII interface" that > > appears to set the SGMII_MODE_ENA bit to 0. > > SGMII_MODE_ENA in PCS1G_MODE_CFG refers to the selection between Cisco > SGMII/QSGMII vs IEEE 802.3 fiber modes. Different autonegotiation code > words being transmitted. It's correct to leave it the way it is. It's > curious that the reference application suggests to set it to 0 for QSGMII. > I suppose that if in-band autoneg isn't enabled in PCS1G_ANEG_CFG, it > doesn't really matter what kind of autoneg is used. > > For SGMII vs QSGMII, the serdes_set_mode() function in > phy-ocelot-serdes.c should set HSIO_HW_CFG_QSGMII_ENA where appropriate. I agree. I think you've answered my most important question, which is whether there's an obvious issue in my Device Tree / understanding. A blunder there can lead to significant loss of time making this work the wrong way. Shuffling datasheets, reference apps, register dumps... > > > Thank you as always for your time, > > > > Colin Foster. > > What bootloader do you use? Do you have VSC8514 PHY initialization of > any sort in the bootloader? U-Boot (now you know my secret next project...) that is basically the default configuration of BeagleBone. Definitely no VSC8514 knowledge by way of SPI > 7512 > MDIO(1) > 8514.