[PATCH net-next 09/12] ARM: dts: r9a06g032: describe MII converter

Clément Léger
2022-04-14T12:26:11Z

Add the MII converter node which describes the MII converter that is
present on the RZ/N1 SoC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 33 ++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 636a6ab31c58..fd174df268e8 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -200,6 +200,39 @@ nand_controller: nand-controller@40102000 {
status = "disabled";
};

+ eth_miic: eth-miic@44030000 {
+ compatible = "renesas,rzn1-miic";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x44030000 0x10000>;
+ clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
+ <&sysctrl R9A06G032_CLK_RGMII_REF>,
+ <&sysctrl R9A06G032_CLK_RMII_REF>,
+ <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
+ clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk_switch_rg";
+ status = "disabled";
+
+ mii_conv0: mii-conv@0 {
+ reg = <0>;
+ };
+
+ mii_conv1: mii-conv@1 {
+ reg = <1>;
+ };
+
+ mii_conv2: mii-conv@2 {
+ reg = <2>;
+ };
+
+ mii_conv3: mii-conv@3 {
+ reg = <3>;
+ };
+
+ mii_conv4: mii-conv@4 {
+ reg = <4>;
+ };
+ };
+
gic: interrupt-controller@44101000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;
--
2.34.1