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In-Reply-To: <20220626192444.29321-2-vfedorenko@novek.ru>
References: <20220626192444.29321-1-vfedorenko@novek.ru> <20220626192444.29321-2-vfedorenko@novek.ru>
Subject: Re: [RFC PATCH v2 1/3] dpll: Add DPLL framework base functions
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Vadim Fedorenko <vadfed@fb.com>, Aya Levin <ayal@nvidia.com>,
        netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-clk@vger.kernel.org
To:     Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Jonathan Lemon <jonathan.lemon@gmail.com>,
        Vadim Fedorenko <vfedorenko@novek.ru>
Date:   Wed, 29 Jun 2022 01:34:37 -0700
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Quoting Vadim Fedorenko (2022-06-26 12:24:42)
> From: Vadim Fedorenko <vadfed@fb.com>
>=20
> DPLL framework is used to represent and configure DPLL devices
> in systems. Each device that has DPLL and can configure sources
> and outputs can use this framework.

Please add more details to the commit text, and possibly introduce some
Documentation/ about this driver subsystem. I'm curious what is
different from drivers/clk/, is it super large frequencies that don't
fit into 32-bits when represented in Hz? Or PLL focused? Or is sub-Hz
required?

Details please!

Does DPLL stand for digital phase locked loop? Again, I have no idea! I
think you get my point.