From: Ido Schimmel <idosch@nvidia.com>
To: netdev@vger.kernel.org
Cc: davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, petrm@nvidia.com, amcohen@nvidia.com,
danieller@nvidia.com, richardcochran@gmail.com, mlxsw@nvidia.com,
Ido Schimmel <idosch@nvidia.com>
Subject: [PATCH net-next 06/15] mlxsw: Set time stamp type as part of config profile
Date: Sun, 24 Jul 2022 11:03:20 +0300 [thread overview]
Message-ID: <20220724080329.2613617-7-idosch@nvidia.com> (raw)
In-Reply-To: <20220724080329.2613617-1-idosch@nvidia.com>
From: Danielle Ratson <danieller@nvidia.com>
The type of time stamp field in the CQE is configured via the
CONFIG_PROFILE command during driver initialization. Add the definition
of the relevant fields to the command's payload and set the type to UTC
for Spectrum-2 and above. This configuration can be done as part of the
preparations to PTP support, as the type of the time stamp will not break
any existing behavior.
Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
---
drivers/net/ethernet/mellanox/mlxsw/cmd.h | 26 +++++++++++++++++++
drivers/net/ethernet/mellanox/mlxsw/core.h | 4 ++-
drivers/net/ethernet/mellanox/mlxsw/pci.c | 7 +++++
.../net/ethernet/mellanox/mlxsw/spectrum.c | 2 ++
4 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mellanox/mlxsw/cmd.h b/drivers/net/ethernet/mellanox/mlxsw/cmd.h
index e5ac5d267348..60232fb8ccd7 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/cmd.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/cmd.h
@@ -689,6 +689,12 @@ MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1);
*/
MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1);
+/* cmd_mbox_config_set_cqe_time_stamp_type
+ * Capability bit. Setting a bit to 1 configures the profile
+ * according to the mailbox contents.
+ */
+MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_time_stamp_type, 0x08, 2, 1);
+
/* cmd_mbox_config_profile_max_vepa_channels
* Maximum number of VEPA channels per port (0 through 16)
* 0 - multi-channel VEPA is disabled
@@ -884,6 +890,26 @@ MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type,
MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties,
0x60, 0, 8, 0x08, 0x00, false);
+enum mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type {
+ /* uSec - 1.024uSec (default). Only bits 15:0 are valid. */
+ MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_USEC,
+ /* FRC - Free Running Clock, units of 1nSec.
+ * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1.
+ */
+ MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_FRC,
+ /* UTC. time_stamp[37:30] = Sec, time_stamp[29:0] = nSec.
+ * Reserved when SwitchX/2, Switch-IB/2 and Spectrum-1.
+ */
+ MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
+};
+
+/* cmd_mbox_config_profile_cqe_time_stamp_type
+ * CQE time_stamp_type for non-mirror-packets.
+ * Configured if set_cqe_time_stamp_type is set.
+ * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1.
+ */
+MLXSW_ITEM32(cmd_mbox, config_profile, cqe_time_stamp_type, 0xB0, 8, 2);
+
/* cmd_mbox_config_profile_cqe_version
* CQE version:
* 0: CQE version is 0
diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h
index a3491ef2aa7e..6b05586052dd 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/core.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.h
@@ -296,7 +296,8 @@ struct mlxsw_config_profile {
used_ar_sec:1,
used_adaptive_routing_group_cap:1,
used_ubridge:1,
- used_kvd_sizes:1;
+ used_kvd_sizes:1,
+ used_cqe_time_stamp_type:1;
u8 max_vepa_channels;
u16 max_mid;
u16 max_pgt;
@@ -319,6 +320,7 @@ struct mlxsw_config_profile {
u32 kvd_linear_size;
u8 kvd_hash_single_parts;
u8 kvd_hash_double_parts;
+ u8 cqe_time_stamp_type;
struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT];
};
diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c
index 41f0f68bc911..57792e87dee2 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
@@ -1267,6 +1267,13 @@ static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
}
+ if (profile->used_cqe_time_stamp_type) {
+ mlxsw_cmd_mbox_config_profile_set_cqe_time_stamp_type_set(mbox,
+ 1);
+ mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type_set(mbox,
+ profile->cqe_time_stamp_type);
+ }
+
return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
}
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
index 209587cf7529..fa48b2631ea8 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
@@ -3411,6 +3411,8 @@ static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
.type = MLXSW_PORT_SWID_TYPE_ETH,
}
},
+ .used_cqe_time_stamp_type = 1,
+ .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
};
static void
--
2.36.1
next prev parent reply other threads:[~2022-07-24 8:05 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-24 8:03 [PATCH net-next 00/15] mlxsw: Spectrum-2 PTP preparations Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 01/15] mlxsw: Rename mlxsw_reg_mtptptp_pack() to mlxsw_reg_mtptpt_pack() Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 02/15] mlxsw: reg: Add MTUTC register's fields for supporting PTP in Spectrum-2 Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 03/15] mlxsw: reg: Add Monitoring Time Precision Correction Port Configuration Register Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 04/15] mlxsw: pci_hw: Add 'time_stamp' and 'time_stamp_type' fields to CQEv2 Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 05/15] mlxsw: cmd: Add UTC related fields to query firmware command Ido Schimmel
2022-07-24 8:03 ` Ido Schimmel [this message]
2022-07-24 8:03 ` [PATCH net-next 07/15] mlxsw: spectrum: Fix the shift of FID field in TX header Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 08/15] mlxsw: resources: Add resource identifier for maximum number of FIDs Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 09/15] mlxsw: Rename 'read_frc_capable' bit to 'read_clock_capable' Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 10/15] mlxsw: spectrum_ptp: Initialize the clock to zero as part of initialization Ido Schimmel
2022-07-24 22:14 ` Richard Cochran
2022-07-24 8:03 ` [PATCH net-next 11/15] mlxsw: pci: Simplify FRC clock reading Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 12/15] mlxsw: spectrum_ptp: Use 'struct mlxsw_sp_ptp_state' per ASIC Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 13/15] mlxsw: spectrum_ptp: Use 'struct mlxsw_sp_ptp_clock' " Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 14/15] mlxsw: spectrum_ptp: Rename mlxsw_sp_ptp_get_message_types() Ido Schimmel
2022-07-24 8:03 ` [PATCH net-next 15/15] mlxsw: spectrum_ptp: Rename mlxsw_sp1_ptp_phc_adjfreq() Ido Schimmel
2022-07-25 13:10 ` [PATCH net-next 00/15] mlxsw: Spectrum-2 PTP preparations patchwork-bot+netdevbpf
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