From: Alexander 'lynxis' Couzens <lynxis@fe80.eu>
To: Paolo Abeni <pabeni@redhat.com>
Cc: Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Russell King <linux@armlinux.org.uk>,
netdev@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
Daniel Golle <daniel@makrotopia.org>
Subject: Re: [PATCH 1/4] net: mediatek: sgmii: fix powering up the SGMII phy
Date: Tue, 23 Aug 2022 16:31:35 +0200 [thread overview]
Message-ID: <20220823163135.013ec257@javelin> (raw)
In-Reply-To: <6f147fbd31980c6155ea6e7deba26d8210ed6afd.camel@redhat.com>
Hi Paolo,
> On Sun, 2022-08-21 at 00:45 +0200, Alexander Couzens wrote:
> > There are cases when the SGMII_PHYA_PWD register contains 0x9 which
> > prevents SGMII from working. The SGMII still shows link but no
> > traffic can flow. Writing 0x0 to the PHYA_PWD register fix the
> > issue. 0x0 was taken from a good working state of the SGMII
> > interface.
>
> do you have access to register documentation? what does 0x9 actually
> mean? is the '0' value based on just empirical evaluation?
I don't have any documentation which describes 0x9.
The datasheet [1] only contains the PHYA_PWD (0x10) bit and the initial
value is 0x10. 0x0 value is based on a register readout without the
patch from a working state.
I've tested it on mt7622 and Daniel Golle on mt7986.
[1] MT7622 Reference Manual, v1.0, 2018-12-19, 1972 pages
Best,
lynxis
next prev parent reply other threads:[~2022-08-23 16:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-20 22:45 [PATCH 0/4] net: mediatek: sgmii: add support to change interface parameter while running Alexander Couzens
2022-08-20 22:45 ` [PATCH 1/4] net: mediatek: sgmii: fix powering up the SGMII phy Alexander Couzens
2022-08-23 13:10 ` Paolo Abeni
2022-08-23 14:31 ` Alexander 'lynxis' Couzens [this message]
2022-08-20 22:45 ` [PATCH 2/4] net: mediatek: sgmii: ensure the SGMII PHY is powered down on configuration Alexander Couzens
2022-08-23 13:18 ` Paolo Abeni
2022-08-23 14:17 ` Alexander 'lynxis' Couzens
2022-08-23 16:38 ` Paolo Abeni
2022-08-20 22:45 ` [PATCH 3/4] net: mediatek: sgmii: mtk_pcs_setup_mode_an: don't rely on register defaults Alexander Couzens
2022-08-23 15:28 ` Russell King (Oracle)
2022-09-02 15:47 ` Alexander 'lynxis' Couzens
2022-09-02 16:36 ` Russell King (Oracle)
2022-08-20 22:45 ` [PATCH 4/4] net: mediatek: sgmii: set the speed according to the phy interface in AN Alexander Couzens
2022-08-23 15:27 ` Russell King (Oracle)
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