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From: kernel test robot <lkp@intel.com>
To: Saeed Mahameed <saeed@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Eric Dumazet <edumazet@google.com>
Cc: kbuild-all@lists.01.org, netdev@vger.kernel.org,
	Saeed Mahameed <saeedm@nvidia.com>,
	Tariq Toukan <tariqt@nvidia.com>, Emeel Hakim <ehakim@nvidia.com>,
	Raed Salem <raeds@nvidia.com>
Subject: Re: [PATCH net-next 09/10] net/mlx5e: Support MACsec offload extended packet number (EPN)
Date: Mon, 12 Sep 2022 11:57:06 +0800	[thread overview]
Message-ID: <202209121134.cIwqQMz7-lkp@intel.com> (raw)
In-Reply-To: <20220911234059.98624-10-saeed@kernel.org>

Hi Saeed,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on net-next/master]

url:    https://github.com/intel-lab-lkp/linux/commits/Saeed-Mahameed/mlx5-MACSec-Extended-packet-number-and-replay-window-offload/20220912-074318
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 169ccf0e40825d9e465863e4707d8e8546d3c3cb
config: powerpc-allmodconfig (https://download.01.org/0day-ci/archive/20220912/202209121134.cIwqQMz7-lkp@intel.com/config)
compiler: powerpc-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/2a128479cc7dc9483c0d677fdcb532ae2ea4b056
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Saeed-Mahameed/mlx5-MACSec-Extended-packet-number-and-replay-window-offload/20220912-074318
        git checkout 2a128479cc7dc9483c0d677fdcb532ae2ea4b056
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/net/ethernet/mellanox/mlx5/core/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   In file included from include/linux/byteorder/big_endian.h:5,
                    from arch/powerpc/include/uapi/asm/byteorder.h:14,
                    from include/asm-generic/bitops/le.h:6,
                    from arch/powerpc/include/asm/bitops.h:336,
                    from include/linux/bitops.h:68,
                    from include/linux/bitmap.h:8,
                    from include/linux/ethtool.h:16,
                    from include/rdma/ib_verbs.h:15,
                    from include/linux/mlx5/device.h:37,
                    from drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c:4:
   drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c: In function 'macsec_aso_build_wqe_ctrl_seg':
>> drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c:1313:73: warning: right shift count >= width of type [-Wshift-count-overflow]
    1313 |                 aso_ctrl->va_h  = cpu_to_be32(macsec_aso->umr->dma_addr >> 32);
         |                                                                         ^~
   include/uapi/linux/byteorder/big_endian.h:40:51: note: in definition of macro '__cpu_to_be32'
      40 | #define __cpu_to_be32(x) ((__force __be32)(__u32)(x))
         |                                                   ^
   drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c:1313:35: note: in expansion of macro 'cpu_to_be32'
    1313 |                 aso_ctrl->va_h  = cpu_to_be32(macsec_aso->umr->dma_addr >> 32);
         |                                   ^~~~~~~~~~~
   drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c: In function 'macsec_aso_build_ctrl':
>> drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c:1389:46: warning: left shift count >= width of type [-Wshift-count-overflow]
    1389 |                 param.bitwise_data = BIT(22) << 32;
         |                                              ^~


vim +1313 drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c

  1305	
  1306	static void macsec_aso_build_wqe_ctrl_seg(struct mlx5e_macsec_aso *macsec_aso,
  1307						  struct mlx5_wqe_aso_ctrl_seg *aso_ctrl,
  1308						  struct mlx5_aso_ctrl_param *param)
  1309	{
  1310		memset(aso_ctrl, 0, sizeof(*aso_ctrl));
  1311		if (macsec_aso->umr->dma_addr) {
  1312			aso_ctrl->va_l  = cpu_to_be32(macsec_aso->umr->dma_addr | ASO_CTRL_READ_EN);
> 1313			aso_ctrl->va_h  = cpu_to_be32(macsec_aso->umr->dma_addr >> 32);
  1314			aso_ctrl->l_key = cpu_to_be32(macsec_aso->umr->mkey);
  1315		}
  1316	
  1317		if (!param)
  1318			return;
  1319	
  1320		aso_ctrl->data_mask_mode = param->data_mask_mode << 6;
  1321		aso_ctrl->condition_1_0_operand = param->condition_1_operand |
  1322							param->condition_0_operand << 4;
  1323		aso_ctrl->condition_1_0_offset = param->condition_1_offset |
  1324							param->condition_0_offset << 4;
  1325		aso_ctrl->data_offset_condition_operand = param->data_offset |
  1326							param->condition_operand << 6;
  1327		aso_ctrl->condition_0_data = cpu_to_be32(param->condition_0_data);
  1328		aso_ctrl->condition_0_mask = cpu_to_be32(param->condition_0_mask);
  1329		aso_ctrl->condition_1_data = cpu_to_be32(param->condition_1_data);
  1330		aso_ctrl->condition_1_mask = cpu_to_be32(param->condition_1_mask);
  1331		aso_ctrl->bitwise_data = cpu_to_be64(param->bitwise_data);
  1332		aso_ctrl->data_mask = cpu_to_be64(param->data_mask);
  1333	}
  1334	
  1335	static int mlx5e_macsec_modify_obj(struct mlx5_core_dev *mdev, struct mlx5_macsec_obj_attrs *attrs,
  1336					   u32 macsec_id)
  1337	{
  1338		u32 in[MLX5_ST_SZ_DW(modify_macsec_obj_in)] = {};
  1339		u32 out[MLX5_ST_SZ_DW(query_macsec_obj_out)];
  1340		u64 modify_field_select = 0;
  1341		void *obj;
  1342		int err;
  1343	
  1344		/* General object fields set */
  1345		MLX5_SET(general_obj_in_cmd_hdr, in, opcode, MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
  1346		MLX5_SET(general_obj_in_cmd_hdr, in, obj_type, MLX5_GENERAL_OBJECT_TYPES_MACSEC);
  1347		MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, macsec_id);
  1348		err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
  1349		if (err) {
  1350			mlx5_core_err(mdev, "Query MACsec object failed (Object id %d), err = %d\n",
  1351				      macsec_id, err);
  1352			return err;
  1353		}
  1354	
  1355		obj = MLX5_ADDR_OF(query_macsec_obj_out, out, macsec_object);
  1356		modify_field_select = MLX5_GET64(macsec_offload_obj, obj, modify_field_select);
  1357	
  1358		/* EPN */
  1359		if (!(modify_field_select & MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP) ||
  1360		    !(modify_field_select & MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB)) {
  1361			mlx5_core_dbg(mdev, "MACsec object field is not modifiable (Object id %d)\n",
  1362				      macsec_id);
  1363			return -EOPNOTSUPP;
  1364		}
  1365	
  1366		obj = MLX5_ADDR_OF(modify_macsec_obj_in, in, macsec_object);
  1367		MLX5_SET64(macsec_offload_obj, obj, modify_field_select,
  1368			   MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP | MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB);
  1369		MLX5_SET(macsec_offload_obj, obj, epn_msb, attrs->epn_state.epn_msb);
  1370		MLX5_SET(macsec_offload_obj, obj, epn_overlap, attrs->epn_state.overlap);
  1371	
  1372		/* General object fields set */
  1373		MLX5_SET(general_obj_in_cmd_hdr, in, opcode, MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
  1374	
  1375		return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
  1376	}
  1377	
  1378	static void macsec_aso_build_ctrl(struct mlx5e_macsec_aso *aso,
  1379					  struct mlx5_wqe_aso_ctrl_seg *aso_ctrl,
  1380					  struct mlx5e_macsec_aso_in *in)
  1381	{
  1382		struct mlx5_aso_ctrl_param param = {};
  1383	
  1384		param.data_mask_mode = MLX5_ASO_DATA_MASK_MODE_BITWISE_64BIT;
  1385		param.condition_0_operand = MLX5_ASO_ALWAYS_TRUE;
  1386		param.condition_1_operand = MLX5_ASO_ALWAYS_TRUE;
  1387		if (in->mode == MLX5_MACSEC_EPN) {
  1388			param.data_offset = MLX5_MACSEC_ASO_REMOVE_FLOW_PKT_CNT_OFFSET;
> 1389			param.bitwise_data = BIT(22) << 32;
  1390			param.data_mask = param.bitwise_data;
  1391		}
  1392	
  1393		macsec_aso_build_wqe_ctrl_seg(aso, aso_ctrl, &param);
  1394	}
  1395	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

  reply	other threads:[~2022-09-12  4:04 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-11 23:40 [PATCH net-next 00/10] mlx5 MACSec Extended packet number and replay window offload Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 01/10] net: macsec: Expose extended packet number (EPN) properties to macsec offload Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 02/10] net/mlx5: Fix fields name prefix in MACsec Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 03/10] net/mlx5e: Fix MACsec initialization error path Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 04/10] net/mlx5e: Fix MACsec initial packet number Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 05/10] net/mlx5: Add ifc bits for MACsec extended packet number (EPN) and replay protection Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 06/10] net/mlx5e: Expose memory key creation (mkey) function Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 07/10] net/mlx5e: Create advanced steering operation (ASO) object for MACsec Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 08/10] net/mlx5e: Move MACsec initialization from profile init stage to profile enable stage Saeed Mahameed
2022-09-11 23:40 ` [PATCH net-next 09/10] net/mlx5e: Support MACsec offload extended packet number (EPN) Saeed Mahameed
2022-09-12  3:57   ` kernel test robot [this message]
2022-09-18 23:00   ` kernel test robot
2022-09-11 23:40 ` [PATCH net-next 10/10] net/mlx5e: Support MACsec offload replay window Saeed Mahameed

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