From: Jakub Kicinski <kuba@kernel.org>
To: Vladimir Oltean <vladimir.oltean@nxp.com>
Cc: netdev@vger.kernel.org, "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
Xiaoliang Yang <xiaoliang.yang_1@nxp.com>,
Claudiu Manoil <claudiu.manoil@nxp.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next 1/2] net: enetc: cache accesses to &priv->si->hw
Date: Thu, 22 Sep 2022 19:42:14 -0700 [thread overview]
Message-ID: <20220922194214.108f7701@kernel.org> (raw)
In-Reply-To: <20220921144349.1529150-1-vladimir.oltean@nxp.com>
On Wed, 21 Sep 2022 17:43:48 +0300 Vladimir Oltean wrote:
> The &priv->si->hw construct dereferences 2 pointers and makes lines
> longer than they need to be, in turn making the code harder to read.
>
> Replace &priv->si->hw accesses with a "hw" variable when there are 2 or
> more accesses within a function that dereference this. This includes
> loops, since &priv->si->hw is a loop invariant.
Could you resend? pw checker could not apply it, it must have depended
on the fixes from net.
prev parent reply other threads:[~2022-09-23 2:42 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 14:43 [PATCH net-next 1/2] net: enetc: cache accesses to &priv->si->hw Vladimir Oltean
2022-09-21 14:43 ` [PATCH net-next 2/2] net: enetc: use common naming scheme for PTGCR and PTGCAPR registers Vladimir Oltean
2022-09-23 2:42 ` Jakub Kicinski [this message]
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