* [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes @ 2022-09-30 19:49 David Yang 2022-09-30 20:28 ` Andrew Lunn 0 siblings, 1 reply; 10+ messages in thread From: David Yang @ 2022-09-30 19:49 UTC (permalink / raw) To: mmyangfl Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, netdev, linux-kernel On device reset all ports are automatically set to RGMII mode. MII mode must be explicitly enabled. If SoC has two Ethernet controllers, by setting both of them into MII mode, the first controller enters GMII mode, while the second controller is effectively disabled. This requires configuring (and maybe enabling) the second controller in the device tree, even though it cannot be used. Signed-off-by: David Yang <mmyangfl@gmail.com> --- drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c index b6be0552a..e2216ce5e 100644 --- a/drivers/net/ethernet/marvell/mv643xx_eth.c +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4"; #define TXQ_COMMAND 0x0048 #define TXQ_FIX_PRIO_CONF 0x004c #define PORT_SERIAL_CONTROL1 0x004c +#define RGMII_EN 0x00000008 #define CLK125_BYPASS_EN 0x00000010 #define TX_BW_RATE 0x0050 #define TX_BW_MTU 0x0058 @@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) out_write: wrlp(mp, PORT_SERIAL_CONTROL, pscr); + + /* If two Ethernet controllers present in the SoC, MII modes follow the + * following matrix: + * + * Port0 Mode Port1 Mode Port0 RGMII_EN Port1 RGMII_EN + * RGMII RGMII 1 1 + * RGMII MII/MMII 1 0 + * MII/MMII RGMII 0 1 + * GMII N/A 0 0 + * + * To enable GMII on Port 0, Port 1 must also disable RGMII_EN too. + */ + if (!phy_interface_is_rgmii(dev->phydev)) + wrlp(mp, PORT_SERIAL_CONTROL1, + rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN); } /* statistics ***************************************************************/ -- 2.35.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes 2022-09-30 19:49 [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes David Yang @ 2022-09-30 20:28 ` Andrew Lunn 2022-09-30 20:39 ` [PATCH v2] " David Yang 2022-09-30 20:47 ` [PATCH] " Yangfl 0 siblings, 2 replies; 10+ messages in thread From: Andrew Lunn @ 2022-09-30 20:28 UTC (permalink / raw) To: David Yang Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, netdev, linux-kernel On Sat, Oct 01, 2022 at 03:49:23AM +0800, David Yang wrote: > On device reset all ports are automatically set to RGMII mode. MII > mode must be explicitly enabled. > > If SoC has two Ethernet controllers, by setting both of them into MII > mode, the first controller enters GMII mode, while the second > controller is effectively disabled. This requires configuring (and > maybe enabling) the second controller in the device tree, even though > it cannot be used. > > Signed-off-by: David Yang <mmyangfl@gmail.com> > --- > drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c > index b6be0552a..e2216ce5e 100644 > --- a/drivers/net/ethernet/marvell/mv643xx_eth.c > +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c > @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4"; > #define TXQ_COMMAND 0x0048 > #define TXQ_FIX_PRIO_CONF 0x004c > #define PORT_SERIAL_CONTROL1 0x004c > +#define RGMII_EN 0x00000008 > #define CLK125_BYPASS_EN 0x00000010 > #define TX_BW_RATE 0x0050 > #define TX_BW_MTU 0x0058 > @@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) > > out_write: > wrlp(mp, PORT_SERIAL_CONTROL, pscr); > + > + /* If two Ethernet controllers present in the SoC, MII modes follow the > + * following matrix: > + * > + * Port0 Mode Port1 Mode Port0 RGMII_EN Port1 RGMII_EN > + * RGMII RGMII 1 1 > + * RGMII MII/MMII 1 0 > + * MII/MMII RGMII 0 1 > + * GMII N/A 0 0 > + * > + * To enable GMII on Port 0, Port 1 must also disable RGMII_EN too. > + */ > + if (!phy_interface_is_rgmii(dev->phydev)) > + wrlp(mp, PORT_SERIAL_CONTROL1, > + rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN); I could be reading this wrong, but doesn't this break the third line: > + * MII/MMII RGMII 0 1 Port 1 probes first, phy_interface is rgmii, so nothing happens, port1 RGMII_EN is left true. Port 0 then probes, MII/MMII is not RGMII, so port1 RGMII_EN is cleared, breaking port1. I think you need to be more specific with the comparison. Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2] net: mv643xx_eth: support MII/GMII/RGMII modes 2022-09-30 20:28 ` Andrew Lunn @ 2022-09-30 20:39 ` David Yang 2022-10-04 8:52 ` Paolo Abeni 2022-09-30 20:47 ` [PATCH] " Yangfl 1 sibling, 1 reply; 10+ messages in thread From: David Yang @ 2022-09-30 20:39 UTC (permalink / raw) To: mmyangfl Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, netdev, linux-kernel Support mode switch properly, which is not available before. If SoC has two Ethernet controllers, by setting both of them into MII mode, the first controller enters GMII mode, while the second controller is effectively disabled. This requires configuring (and maybe enabling) the second controller in the device tree, even though it cannot be used. Signed-off-by: David Yang <mmyangfl@gmail.com> --- v2: clarify modes work on controllers, read default value from PSC1 drivers/net/ethernet/marvell/mv643xx_eth.c | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c index b6be0552a..ddaccc979 100644 --- a/drivers/net/ethernet/marvell/mv643xx_eth.c +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4"; #define TXQ_COMMAND 0x0048 #define TXQ_FIX_PRIO_CONF 0x004c #define PORT_SERIAL_CONTROL1 0x004c +#define RGMII_EN 0x00000008 #define CLK125_BYPASS_EN 0x00000010 #define TX_BW_RATE 0x0050 #define TX_BW_MTU 0x0058 @@ -1215,6 +1216,7 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) DISABLE_AUTO_NEG_SPEED_GMII | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | DISABLE_AUTO_NEG_FOR_DUPLEX; + u32 psc1r = rdlp(mp, PORT_SERIAL_CONTROL1); if (dev->phydev->autoneg == AUTONEG_ENABLE) { /* enable auto negotiation */ @@ -1245,6 +1247,30 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) out_write: wrlp(mp, PORT_SERIAL_CONTROL, pscr); + + /* If two Ethernet controllers present in the SoC, and both of them have + * RGMII_EN disabled, the first controller will be in GMII mode and the + * second one is effectively disabled, instead of two MII interfaces. + * + * To enable GMII in the first controller, the second one must also be + * configured (and may be enabled) with RGMII_EN disabled too, even + * though it cannot be used at all. + */ + switch (dev->phydev->interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + wrlp(mp, PORT_SERIAL_CONTROL1, psc1r & ~RGMII_EN); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + wrlp(mp, PORT_SERIAL_CONTROL1, psc1r | RGMII_EN); + break; + default: + /* Unknown; don't touch */ + break; + } } /* statistics ***************************************************************/ @@ -2975,11 +3001,15 @@ static int get_phy_mode(struct mv643xx_eth_private *mp) if (dev->of_node) err = of_get_phy_mode(dev->of_node, &iface); - /* Historical default if unspecified. We could also read/write - * the interface state in the PSC1 + /* Read the interface state in the PSC1. + * + * Modes of two devices may interact; see comments in + * mv643xx_eth_adjust_link. Currently there is no way to detect another + * device within this scope; blindly set MII here. */ if (!dev->of_node || err) - iface = PHY_INTERFACE_MODE_GMII; + iface = rdlp(mp, PORT_SERIAL_CONTROL1) & RGMII_EN ? + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; return iface; } -- 2.35.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2] net: mv643xx_eth: support MII/GMII/RGMII modes 2022-09-30 20:39 ` [PATCH v2] " David Yang @ 2022-10-04 8:52 ` Paolo Abeni 0 siblings, 0 replies; 10+ messages in thread From: Paolo Abeni @ 2022-10-04 8:52 UTC (permalink / raw) To: David Yang Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, netdev, linux-kernel Hello, On Sat, 2022-10-01 at 04:39 +0800, David Yang wrote: > Support mode switch properly, which is not available before. > > If SoC has two Ethernet controllers, by setting both of them into MII > mode, the first controller enters GMII mode, while the second > controller is effectively disabled. This requires configuring (and > maybe enabling) the second controller in the device tree, even though > it cannot be used. > > Signed-off-by: David Yang <mmyangfl@gmail.com> It looks like that despite the subj change, this is superseded by: https://patchwork.kernel.org/project/netdevbpf/patch/20221001174524.2007912-1-mmyangfl@gmail.com/ I'm updating the PW accordingly. Please let me know if you intended otherwise. Thanks, Paolo ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes 2022-09-30 20:28 ` Andrew Lunn 2022-09-30 20:39 ` [PATCH v2] " David Yang @ 2022-09-30 20:47 ` Yangfl 2022-09-30 21:05 ` Andrew Lunn 1 sibling, 1 reply; 10+ messages in thread From: Yangfl @ 2022-09-30 20:47 UTC (permalink / raw) To: Andrew Lunn Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, netdev, linux-kernel Andrew Lunn <andrew@lunn.ch> 于2022年10月1日周六 04:28写道： > > On Sat, Oct 01, 2022 at 03:49:23AM +0800, David Yang wrote: > > On device reset all ports are automatically set to RGMII mode. MII > > mode must be explicitly enabled. > > > > If SoC has two Ethernet controllers, by setting both of them into MII > > mode, the first controller enters GMII mode, while the second > > controller is effectively disabled. This requires configuring (and > > maybe enabling) the second controller in the device tree, even though > > it cannot be used. > > > > Signed-off-by: David Yang <mmyangfl@gmail.com> > > --- > > drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c > > index b6be0552a..e2216ce5e 100644 > > --- a/drivers/net/ethernet/marvell/mv643xx_eth.c > > +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c > > @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4"; > > #define TXQ_COMMAND 0x0048 > > #define TXQ_FIX_PRIO_CONF 0x004c > > #define PORT_SERIAL_CONTROL1 0x004c > > +#define RGMII_EN 0x00000008 > > #define CLK125_BYPASS_EN 0x00000010 > > #define TX_BW_RATE 0x0050 > > #define TX_BW_MTU 0x0058 > > @@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) > > > > out_write: > > wrlp(mp, PORT_SERIAL_CONTROL, pscr); > > + > > + /* If two Ethernet controllers present in the SoC, MII modes follow the > > + * following matrix: > > + * > > + * Port0 Mode Port1 Mode Port0 RGMII_EN Port1 RGMII_EN > > + * RGMII RGMII 1 1 > > + * RGMII MII/MMII 1 0 > > + * MII/MMII RGMII 0 1 > > + * GMII N/A 0 0 > > + * > > + * To enable GMII on Port 0, Port 1 must also disable RGMII_EN too. > > + */ > > + if (!phy_interface_is_rgmii(dev->phydev)) > > + wrlp(mp, PORT_SERIAL_CONTROL1, > > + rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN); > > I could be reading this wrong, but doesn't this break the third line: > > > + * MII/MMII RGMII 0 1 > > Port 1 probes first, phy_interface is rgmii, so nothing happens, port1 > RGMII_EN is left true. > > Port 0 then probes, MII/MMII is not RGMII, so port1 RGMII_EN is > cleared, breaking port1. > > I think you need to be more specific with the comparison. > > Andrew Oh, I see. So you mean "phy-mode" property should belong to controller, not port? I thought one controller can have at most one port. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes 2022-09-30 20:47 ` [PATCH] " Yangfl @ 2022-09-30 21:05 ` Andrew Lunn 2022-09-30 21:35 ` [PATCH v3] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood David Yang 0 siblings, 1 reply; 10+ messages in thread From: Andrew Lunn @ 2022-09-30 21:05 UTC (permalink / raw) To: Yangfl Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, netdev, linux-kernel On Sat, Oct 01, 2022 at 04:47:42AM +0800, Yangfl wrote: > Andrew Lunn <andrew@lunn.ch> 于2022年10月1日周六 04:28写道： > > > > On Sat, Oct 01, 2022 at 03:49:23AM +0800, David Yang wrote: > > > On device reset all ports are automatically set to RGMII mode. MII > > > mode must be explicitly enabled. > > > > > > If SoC has two Ethernet controllers, by setting both of them into MII > > > mode, the first controller enters GMII mode, while the second > > > controller is effectively disabled. This requires configuring (and > > > maybe enabling) the second controller in the device tree, even though > > > it cannot be used. > > > > > > Signed-off-by: David Yang <mmyangfl@gmail.com> > > > --- > > > drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++ > > > 1 file changed, 16 insertions(+) > > > > > > diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c > > > index b6be0552a..e2216ce5e 100644 > > > --- a/drivers/net/ethernet/marvell/mv643xx_eth.c > > > +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c > > > @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4"; > > > #define TXQ_COMMAND 0x0048 > > > #define TXQ_FIX_PRIO_CONF 0x004c > > > #define PORT_SERIAL_CONTROL1 0x004c > > > +#define RGMII_EN 0x00000008 > > > #define CLK125_BYPASS_EN 0x00000010 > > > #define TX_BW_RATE 0x0050 > > > #define TX_BW_MTU 0x0058 > > > @@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) > > > > > > out_write: > > > wrlp(mp, PORT_SERIAL_CONTROL, pscr); > > > + > > > + /* If two Ethernet controllers present in the SoC, MII modes follow the > > > + * following matrix: > > > + * > > > + * Port0 Mode Port1 Mode Port0 RGMII_EN Port1 RGMII_EN > > > + * RGMII RGMII 1 1 > > > + * RGMII MII/MMII 1 0 > > > + * MII/MMII RGMII 0 1 > > > + * GMII N/A 0 0 > > > + * > > > + * To enable GMII on Port 0, Port 1 must also disable RGMII_EN too. > > > + */ > > > + if (!phy_interface_is_rgmii(dev->phydev)) > > > + wrlp(mp, PORT_SERIAL_CONTROL1, > > > + rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN); > > > > I could be reading this wrong, but doesn't this break the third line: > > > > > + * MII/MMII RGMII 0 1 > > > > Port 1 probes first, phy_interface is rgmii, so nothing happens, port1 > > RGMII_EN is left true. > > > > Port 0 then probes, MII/MMII is not RGMII, so port1 RGMII_EN is > > cleared, breaking port1. > > > > I think you need to be more specific with the comparison. > > > > Andrew > > Oh, I see. So you mean "phy-mode" property should belong to > controller, not port? I thought one controller can have at most one > port. If you look at mv643xx_eth_shared_of_probe(), it appears a controller can have multiple ports. And: if (dev_num == 3) { dev_err(&pdev->dev, "too many ports registered\n"); return -EINVAL; } I don't know the details? Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood 2022-09-30 21:05 ` Andrew Lunn @ 2022-09-30 21:35 ` David Yang 2022-09-30 22:25 ` [PATCH v4] " David Yang 0 siblings, 1 reply; 10+ messages in thread From: David Yang @ 2022-09-30 21:35 UTC (permalink / raw) To: mmyangfl Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, netdev, linux-kernel Support mode switch properly, which is not available before. If SoC has two Ethernet controllers, by setting both of them into MII mode, the first controller enters GMII mode, while the second controller is effectively disabled. This requires configuring (and maybe enabling) the second controller in the device tree, even though it cannot be used. Signed-off-by: David Yang <mmyangfl@gmail.com> --- v2: clarify modes work on controllers, read default value from PSC1 v3: Kirkwood only drivers/net/ethernet/marvell/mv643xx_eth.c | 48 ++++++++++++++++++++-- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c index b6be0552a..355bb8ba7 100644 --- a/drivers/net/ethernet/marvell/mv643xx_eth.c +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4"; #define TXQ_COMMAND 0x0048 #define TXQ_FIX_PRIO_CONF 0x004c #define PORT_SERIAL_CONTROL1 0x004c +#define RGMII_EN 0x00000008 #define CLK125_BYPASS_EN 0x00000010 #define TX_BW_RATE 0x0050 #define TX_BW_MTU 0x0058 @@ -367,6 +368,7 @@ struct mv643xx_eth_private { struct mv643xx_eth_shared_private *shared; void __iomem *base; int port_num; + bool kirkwood; struct net_device *dev; @@ -1215,6 +1217,7 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) DISABLE_AUTO_NEG_SPEED_GMII | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | DISABLE_AUTO_NEG_FOR_DUPLEX; + u32 psc1r; if (dev->phydev->autoneg == AUTONEG_ENABLE) { /* enable auto negotiation */ @@ -1245,6 +1248,36 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) out_write: wrlp(mp, PORT_SERIAL_CONTROL, pscr); + + if (mp->kirkwood) { + psc1r = rdlp(mp, PORT_SERIAL_CONTROL1); + /* On Kirkwood with two Ethernet controllers, if both of them + * have RGMII_EN disabled, the first controller will be in GMII + * mode and the second one is effectively disabled, instead of + * two MII interfaces. + * + * To enable GMII in the first controller, the second one must + * also be configured (and may be enabled) with RGMII_EN + * disabled too, even though it cannot be used at all. + */ + switch (dev->phydev->interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + psc1r &= ~RGMII_EN; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + psc1r |= RGMII_EN; + break; + default: + /* Unknown; don't touch */ + break; + } + + wrlp(mp, PORT_SERIAL_CONTROL1, psc1r); + } } /* statistics ***************************************************************/ @@ -2975,11 +3008,16 @@ static int get_phy_mode(struct mv643xx_eth_private *mp) if (dev->of_node) err = of_get_phy_mode(dev->of_node, &iface); - /* Historical default if unspecified. We could also read/write - * the interface state in the PSC1 + /* Read the interface state in the PSC1. + * + * Modes of two devices may interact on Kirkwood. Currently there is no + * way to detect another device within this scope; blindly set MII + * here. */ if (!dev->of_node || err) - iface = PHY_INTERFACE_MODE_GMII; + iface = rdlp(mp, PORT_SERIAL_CONTROL1) & RGMII_EN ? + PHY_INTERFACE_MODE_RGMII : mp->kirkwood ? + PHY_INTERFACE_MODE_MII : PHY_INTERFACE_MODE_GMII; return iface; } @@ -3124,9 +3162,11 @@ static int mv643xx_eth_probe(struct platform_device *pdev) * all other SoCs/System Controllers using this driver. */ if (of_device_is_compatible(pdev->dev.of_node, - "marvell,kirkwood-eth-port")) + "marvell,kirkwood-eth-port")) { wrlp(mp, PORT_SERIAL_CONTROL1, rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN); + mp->kirkwood = 1; + } /* * Start with a default rate, and if there is a clock, allow -- 2.35.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood 2022-09-30 21:35 ` [PATCH v3] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood David Yang @ 2022-09-30 22:25 ` David Yang 2022-10-01 0:59 ` Jakub Kicinski 0 siblings, 1 reply; 10+ messages in thread From: David Yang @ 2022-09-30 22:25 UTC (permalink / raw) To: mmyangfl Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, netdev, linux-kernel Support mode switch properly, which is not available before. If SoC has two Ethernet controllers, by setting both of them into MII mode, the first controller enters GMII mode, while the second controller is effectively disabled. This requires configuring (and maybe enabling) the second controller in the device tree, even though it cannot be used. Signed-off-by: David Yang <mmyangfl@gmail.com> --- v2: clarify modes work on controllers, read default value from PSC1 v3: Kirkwood only v4: cleanup drivers/net/ethernet/marvell/mv643xx_eth.c | 57 +++++++++++++++++++--- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c index b6be0552a..4d4ee36b5 100644 --- a/drivers/net/ethernet/marvell/mv643xx_eth.c +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4"; #define TXQ_COMMAND 0x0048 #define TXQ_FIX_PRIO_CONF 0x004c #define PORT_SERIAL_CONTROL1 0x004c +#define RGMII_EN 0x00000008 #define CLK125_BYPASS_EN 0x00000010 #define TX_BW_RATE 0x0050 #define TX_BW_MTU 0x0058 @@ -1215,6 +1216,7 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) DISABLE_AUTO_NEG_SPEED_GMII | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | DISABLE_AUTO_NEG_FOR_DUPLEX; + u32 psc1r; if (dev->phydev->autoneg == AUTONEG_ENABLE) { /* enable auto negotiation */ @@ -1245,6 +1247,38 @@ static void mv643xx_eth_adjust_link(struct net_device *dev) out_write: wrlp(mp, PORT_SERIAL_CONTROL, pscr); + + if (dev->dev->of_node && + of_device_is_compatible(dev->dev->of_node, + "marvell,kirkwood-eth-port")) { + psc1r = rdlp(mp, PORT_SERIAL_CONTROL1); + /* On Kirkwood with two Ethernet controllers, if both of them + * have RGMII_EN disabled, the first controller will be in GMII + * mode and the second one is effectively disabled, instead of + * two MII interfaces. + * + * To enable GMII in the first controller, the second one must + * also be configured (and may be enabled) with RGMII_EN + * disabled too, even though it cannot be used at all. + */ + switch (dev->phydev->interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + psc1r &= ~RGMII_EN; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + psc1r |= RGMII_EN; + break; + default: + /* Unknown; don't touch */ + break; + } + + wrlp(mp, PORT_SERIAL_CONTROL1, psc1r); + } } /* statistics ***************************************************************/ @@ -2972,15 +3006,26 @@ static int get_phy_mode(struct mv643xx_eth_private *mp) phy_interface_t iface; int err; - if (dev->of_node) + if (dev->of_node) { err = of_get_phy_mode(dev->of_node, &iface); + if (!err) + return iface; + } + + /* Read the interface state in the PSC1 */ + if (rdlp(mp, PORT_SERIAL_CONTROL1) & RGMII_EN) + return PHY_INTERFACE_MODE_RGMII; - /* Historical default if unspecified. We could also read/write - * the interface state in the PSC1 + /* Modes of two devices may interact on Kirkwood. Currently there is no + * way to detect another device within this scope; blindly set MII + * here. */ - if (!dev->of_node || err) - iface = PHY_INTERFACE_MODE_GMII; - return iface; + if (dev->of_node && + of_device_is_compatible(dev->of_node, "marvell,kirkwood-eth")) + return PHY_INTERFACE_MODE_MII; + + /* Historical default if unspecified */ + return PHY_INTERFACE_MODE_GMII; } static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, -- 2.35.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood 2022-09-30 22:25 ` [PATCH v4] " David Yang @ 2022-10-01 0:59 ` Jakub Kicinski 2022-10-01 8:42 ` [PATCH v5] " David Yang 0 siblings, 1 reply; 10+ messages in thread From: Jakub Kicinski @ 2022-10-01 0:59 UTC (permalink / raw) To: David Yang Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Paolo Abeni, netdev On Sat, 1 Oct 2022 06:25:39 +0800 David Yang wrote: > Support mode switch properly, which is not available before. > > If SoC has two Ethernet controllers, by setting both of them into MII > mode, the first controller enters GMII mode, while the second > controller is effectively disabled. This requires configuring (and > maybe enabling) the second controller in the device tree, even though > it cannot be used. Well, this version does not build: drivers/net/ethernet/marvell/mv643xx_eth.c:1252:38: error: member reference type 'struct device' is not a pointer; did you mean to use '.'? of_device_is_compatible(dev->dev->of_node, ~~~~~~~~^~ . ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v5] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood 2022-10-01 0:59 ` Jakub Kicinski @ 2022-10-01 8:42 ` David Yang 0 siblings, 0 replies; 10+ messages in thread From: David Yang @ 2022-10-01 8:42 UTC (permalink / raw) To: mmyangfl Cc: Sebastian Hesselbarth, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, netdev, linux-kernel Support mode switch properly, which is not available before. If SoC has two Ethernet controllers, by setting both of them into MII mode, the first controller enters GMII mode, while the second controller is effectively disabled. This requires configuring (and maybe enabling) the second controller in the device tree, even though it cannot be used. Signed-off-by: David Yang <mmyangfl@gmail.com> --- v2: clarify modes work on controllers, read default value from PSC1 v3: Kirkwood only v4: cleanup v5: test on 88f6282 drivers/net/ethernet/marvell/mv643xx_eth.c | 49 ++++++++++++++++++---- include/linux/mv643xx_eth.h | 1 + 2 files changed, 43 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c index b6be0552a..ed674c512 100644 --- a/drivers/net/ethernet/marvell/mv643xx_eth.c +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] = "1.4"; #define TXQ_COMMAND 0x0048 #define TXQ_FIX_PRIO_CONF 0x004c #define PORT_SERIAL_CONTROL1 0x004c +#define RGMII_EN 0x00000008 #define CLK125_BYPASS_EN 0x00000010 #define TX_BW_RATE 0x0050 #define TX_BW_MTU 0x0058 @@ -2761,6 +2762,8 @@ static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev, mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr); mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size); + of_get_phy_mode(pnp, &ppd.interface); + ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0); if (!ppd.phy_node) { ppd.phy_addr = MV643XX_ETH_PHY_NONE; @@ -3092,6 +3095,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev) struct mv643xx_eth_private *mp; struct net_device *dev; struct phy_device *phydev = NULL; + u32 psc1r; int err, irq; pd = dev_get_platdata(&pdev->dev); @@ -3119,14 +3123,45 @@ static int mv643xx_eth_probe(struct platform_device *pdev) mp->dev = dev; - /* Kirkwood resets some registers on gated clocks. Especially - * CLK125_BYPASS_EN must be cleared but is not available on - * all other SoCs/System Controllers using this driver. - */ if (of_device_is_compatible(pdev->dev.of_node, - "marvell,kirkwood-eth-port")) - wrlp(mp, PORT_SERIAL_CONTROL1, - rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN); + "marvell,kirkwood-eth-port")) { + psc1r = rdlp(mp, PORT_SERIAL_CONTROL1); + + /* Kirkwood resets some registers on gated clocks. Especially + * CLK125_BYPASS_EN must be cleared but is not available on + * all other SoCs/System Controllers using this driver. + */ + psc1r &= ~CLK125_BYPASS_EN; + + /* On Kirkwood with two Ethernet controllers, if both of them + * have RGMII_EN disabled, the first controller will be in GMII + * mode and the second one is effectively disabled, instead of + * two MII interfaces. + * + * To enable GMII in the first controller, the second one must + * also be configured (and may be enabled) with RGMII_EN + * disabled too, even though it cannot be used at all. + */ + switch (pd->interface) { + /* Use internal to denote second controller being disabled */ + case PHY_INTERFACE_MODE_INTERNAL: + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + psc1r &= ~RGMII_EN; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + psc1r |= RGMII_EN; + break; + default: + /* Unknown; don't touch */ + break; + } + + wrlp(mp, PORT_SERIAL_CONTROL1, psc1r); + } /* * Start with a default rate, and if there is a clock, allow diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h index 3682ae75c..14dc448f0 100644 --- a/include/linux/mv643xx_eth.h +++ b/include/linux/mv643xx_eth.h @@ -59,6 +59,7 @@ struct mv643xx_eth_platform_data { */ int speed; int duplex; + phy_interface_t interface; /* * How many RX/TX queues to use. -- 2.35.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-10-04 8:52 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-09-30 19:49 [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes David Yang 2022-09-30 20:28 ` Andrew Lunn 2022-09-30 20:39 ` [PATCH v2] " David Yang 2022-10-04 8:52 ` Paolo Abeni 2022-09-30 20:47 ` [PATCH] " Yangfl 2022-09-30 21:05 ` Andrew Lunn 2022-09-30 21:35 ` [PATCH v3] net: mv643xx_eth: support MII/GMII/RGMII modes for Kirkwood David Yang 2022-09-30 22:25 ` [PATCH v4] " David Yang 2022-10-01 0:59 ` Jakub Kicinski 2022-10-01 8:42 ` [PATCH v5] " David Yang
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