* [PATCH net-next] r8169: fix rtl8125b dmar pte write access not set error
@ 2022-10-03 6:46 Chunhao Lin
2022-10-04 0:05 ` Jakub Kicinski
0 siblings, 1 reply; 3+ messages in thread
From: Chunhao Lin @ 2022-10-03 6:46 UTC (permalink / raw)
To: hkallweit1; +Cc: netdev, nic_swsd, kuba, grundler, Chunhao Lin
When close device, rx will be enabled if wol is enabeld. When open device
it will cause rx to dma to wrong address after pci_set_master().
In this patch, driver will disable tx/rx when close device. If wol is
eanbled only enable rx filter and disable rxdv_gate to let hardware can
receive packet to fifo but not to dma it.
Signed-off-by: Chunhao Lin <hau@realtek.com>
---
drivers/net/ethernet/realtek/r8169_main.c | 57 +++++++++++------------
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index a73d061d9fcb..25d02b0467b9 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -2210,28 +2210,6 @@ static int rtl_set_mac_address(struct net_device *dev, void *p)
return 0;
}
-static void rtl_wol_enable_rx(struct rtl8169_private *tp)
-{
- if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
- RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
- AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
-}
-
-static void rtl_prepare_power_down(struct rtl8169_private *tp)
-{
- if (tp->dash_type != RTL_DASH_NONE)
- return;
-
- if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
- tp->mac_version == RTL_GIGA_MAC_VER_33)
- rtl_ephy_write(tp, 0x19, 0xff64);
-
- if (device_may_wakeup(tp_to_dev(tp))) {
- phy_speed_down(tp->phydev, false);
- rtl_wol_enable_rx(tp);
- }
-}
-
static void rtl_init_rxcfg(struct rtl8169_private *tp)
{
switch (tp->mac_version) {
@@ -2455,6 +2433,30 @@ static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
rtl_wait_txrx_fifo_empty(tp);
}
+static void rtl_wol_enable_rx(struct rtl8169_private *tp)
+{
+ if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
+ RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
+ AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
+
+ rtl_disable_rxdvgate(tp);
+}
+
+static void rtl_prepare_power_down(struct rtl8169_private *tp)
+{
+ if (tp->dash_type != RTL_DASH_NONE)
+ return;
+
+ if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
+ tp->mac_version == RTL_GIGA_MAC_VER_33)
+ rtl_ephy_write(tp, 0x19, 0xff64);
+
+ if (device_may_wakeup(tp_to_dev(tp))) {
+ phy_speed_down(tp->phydev, false);
+ rtl_wol_enable_rx(tp);
+ }
+}
+
static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
{
u32 val = TX_DMA_BURST << TxDMAShift |
@@ -3872,7 +3874,7 @@ static void rtl8169_tx_clear(struct rtl8169_private *tp)
netdev_reset_queue(tp->dev);
}
-static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
+static void rtl8169_cleanup(struct rtl8169_private *tp)
{
napi_disable(&tp->napi);
@@ -3884,9 +3886,6 @@ static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
rtl_rx_close(tp);
- if (going_down && tp->dev->wol_enabled)
- goto no_reset;
-
switch (tp->mac_version) {
case RTL_GIGA_MAC_VER_28:
case RTL_GIGA_MAC_VER_31:
@@ -3907,7 +3906,7 @@ static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
}
rtl_hw_reset(tp);
-no_reset:
+
rtl8169_tx_clear(tp);
rtl8169_init_ring_indexes(tp);
}
@@ -3918,7 +3917,7 @@ static void rtl_reset_work(struct rtl8169_private *tp)
netif_stop_queue(tp->dev);
- rtl8169_cleanup(tp, false);
+ rtl8169_cleanup(tp);
for (i = 0; i < NUM_RX_DESC; i++)
rtl8169_mark_to_asic(tp->RxDescArray + i);
@@ -4604,7 +4603,7 @@ static void rtl8169_down(struct rtl8169_private *tp)
pci_clear_master(tp->pci_dev);
rtl_pci_commit(tp);
- rtl8169_cleanup(tp, true);
+ rtl8169_cleanup(tp);
rtl_disable_exit_l1(tp);
rtl_prepare_power_down(tp);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH net-next] r8169: fix rtl8125b dmar pte write access not set error
2022-10-03 6:46 [PATCH net-next] r8169: fix rtl8125b dmar pte write access not set error Chunhao Lin
@ 2022-10-04 0:05 ` Jakub Kicinski
2022-10-04 5:52 ` Hau
0 siblings, 1 reply; 3+ messages in thread
From: Jakub Kicinski @ 2022-10-04 0:05 UTC (permalink / raw)
To: Chunhao Lin; +Cc: hkallweit1, netdev, nic_swsd, grundler
On Mon, 3 Oct 2022 14:46:20 +0800 Chunhao Lin wrote:
> When close device, rx will be enabled if wol is enabeld. When open device
> it will cause rx to dma to wrong address after pci_set_master().
>
> In this patch, driver will disable tx/rx when close device. If wol is
> eanbled only enable rx filter and disable rxdv_gate to let hardware can
> receive packet to fifo but not to dma it.
Sounds like a fix, could you resend with a Fixes tag and [PATCH net]
designation? net-next is for new features and refactoring, net for
fixes.
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH net-next] r8169: fix rtl8125b dmar pte write access not set error
2022-10-04 0:05 ` Jakub Kicinski
@ 2022-10-04 5:52 ` Hau
0 siblings, 0 replies; 3+ messages in thread
From: Hau @ 2022-10-04 5:52 UTC (permalink / raw)
To: Jakub Kicinski
Cc: hkallweit1@gmail.com, netdev@vger.kernel.org, nic_swsd,
grundler@chromium.org
> On Mon, 3 Oct 2022 14:46:20 +0800 Chunhao Lin wrote:
> > When close device, rx will be enabled if wol is enabeld. When open
> > device it will cause rx to dma to wrong address after pci_set_master().
> >
> > In this patch, driver will disable tx/rx when close device. If wol is
> > eanbled only enable rx filter and disable rxdv_gate to let hardware
> > can receive packet to fifo but not to dma it.
>
> Sounds like a fix, could you resend with a Fixes tag and [PATCH net]
> designation? net-next is for new features and refactoring, net for fixes.
I will resend this patch to [PATCH net]. Thanks.
> ------Please consider the environment before printing this e-mail.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-10-03 6:46 [PATCH net-next] r8169: fix rtl8125b dmar pte write access not set error Chunhao Lin
2022-10-04 0:05 ` Jakub Kicinski
2022-10-04 5:52 ` Hau
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