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b=gCrBOK4i+R57re92w6HwP5OLlSGwbFIE6nS9YY8mRyMsdg6Eh0upmF1cc0ra38GlvJhlG4ji7zegiLZexOhn/+GiQzHXG6Y7oJZ6CPOx+aVCOltqzARAgSuEXdQS1pxfa9qSfgRxHFsDG+wAtq4X70olna43cs1WSqozpS3NB3Q= Received: from VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) by DB9PR04MB8282.eurprd04.prod.outlook.com (2603:10a6:10:24a::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.15; Mon, 10 Oct 2022 11:57:31 +0000 Received: from VI1PR04MB5136.eurprd04.prod.outlook.com ([fe80::a67a:849c:aeff:cad1]) by VI1PR04MB5136.eurprd04.prod.outlook.com ([fe80::a67a:849c:aeff:cad1%7]) with mapi id 15.20.5709.015; Mon, 10 Oct 2022 11:57:31 +0000 From: Vladimir Oltean To: Sasha Levin CC: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , Paolo Abeni , Claudiu Manoil , "alexandre.belloni@bootlin.com" , "UNGLinuxDriver@microchip.com" , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "netdev@vger.kernel.org" Subject: Re: [PATCH AUTOSEL 6.0 12/77] net: mscc: ocelot: adjust forwarding domain for CPU ports in a LAG Thread-Topic: [PATCH AUTOSEL 6.0 12/77] net: mscc: ocelot: adjust forwarding domain for CPU ports in a LAG Thread-Index: AQHY3CurwLBO2xP21UOnbEjE4uvfrq4HhpyA Date: Mon, 10 Oct 2022 11:57:31 +0000 Message-ID: <20221010115731.qjji7bgt53rusvzf@skbuf> References: <20221009220754.1214186-1-sashal@kernel.org> <20221009220754.1214186-12-sashal@kernel.org> In-Reply-To: <20221009220754.1214186-12-sashal@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0ff102db-4c44-43e9-0b87-08daaab69cd5 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Oct 2022 11:57:31.8167 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: bC+0ttXE78BEtGW/hLKXDCjgaVIq4KPq7q+YuEr/NOCjfJYHpUnP02GYUpywyu7ZsrI2xFtiaU1TkG8jTdhXwA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8282 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Sun, Oct 09, 2022 at 06:06:49PM -0400, Sasha Levin wrote: > From: Vladimir Oltean >=20 > [ Upstream commit 291ac1517af58670740528466ccebe3caefb9093 ] >=20 > Currently when we have 2 CPU ports configured for DSA tag_8021q mode and > we put them in a LAG, a PGID dump looks like this: >=20 > PGID_SRC[0] =3D ports 4, > PGID_SRC[1] =3D ports 4, > PGID_SRC[2] =3D ports 4, > PGID_SRC[3] =3D ports 4, > PGID_SRC[4] =3D ports 0, 1, 2, 3, 4, 5, > PGID_SRC[5] =3D no ports >=20 > (ports 0-3 are user ports, ports 4 and 5 are CPU ports) >=20 > There are 2 problems with the configuration above: >=20 > - user ports should enable forwarding towards both CPU ports, not just 4, > and the aggregation PGIDs should prune one CPU port or the other from > the destination port mask, based on a hash computed from packet headers= . >=20 > - CPU ports should not be allowed to forward towards themselves and also > not towards other ports in the same LAG as themselves >=20 > The first problem requires fixing up the PGID_SRC of user ports, when > ocelot_port_assigned_dsa_8021q_cpu_mask() is called. We need to say that > when a user port is assigned to a tag_8021q CPU port and that port is in > a LAG, it should forward towards all ports in that LAG. >=20 > The second problem requires fixing up the PGID_SRC of port 4, to remove > ports 4 and 5 (in a LAG) from the allowed destinations. >=20 > After this change, the PGID source masks look as follows: >=20 > PGID_SRC[0] =3D ports 4, 5, > PGID_SRC[1] =3D ports 4, 5, > PGID_SRC[2] =3D ports 4, 5, > PGID_SRC[3] =3D ports 4, 5, > PGID_SRC[4] =3D ports 0, 1, 2, 3, > PGID_SRC[5] =3D no ports >=20 > Note that PGID_SRC[5] still looks weird (it should say "0, 1, 2, 3" just > like PGID_SRC[4] does), but I've tested forwarding through this CPU port > and it doesn't seem like anything is affected (it appears that PGID_SRC[4= ] > is being looked up on forwarding from the CPU, since both ports 4 and 5 > have logical port ID 4). The reason why it looks weird is because > we've never called ocelot_port_assign_dsa_8021q_cpu() for any user port > towards port 5 (all user ports are assigned to port 4 which is in a LAG > with 5). >=20 > Since things aren't broken, I'm willing to leave it like that for now > and just document the oddity. >=20 > Signed-off-by: Vladimir Oltean > Signed-off-by: Paolo Abeni > Signed-off-by: Sasha Levin > --- Not needed for stable kernels, please drop, thanks.=