Re: mv88e6321, dual cpu port

[Vladimir Oltean <olteanv@gmail.com>]

On Thu, Feb 16, 2023 at 01:59:22PM +0100, Andrew Lunn wrote:
> On Thu, Feb 16, 2023 at 02:50:40PM +0200, Vladimir Oltean wrote:
> > On Thu, Feb 16, 2023 at 12:20:24PM +0100, Angelo Dureghello wrote:
> > > Still data passes all trough port6, even when i ping from
> > > host PC to port4. I was expecting instead to see port5
> > > statistics increasing.
> > 
> > > # configure the bridge
> > > ip addr add 192.0.2.1/25 dev br0
> > > ip addr add 192.0.2.129/25 dev br1
> > 
> > In this configuration you're supposed to put an IP address on the fec2
> > interface (eth1), not on br1.
> > 
> > br1 will handle offloaded forwarding between port5 and the external
> > ports (port3, port4). It doesn't need an IP address. In fact, if you
> > give it an IP address, you will make the sent packets go through the br1
> > interface, which does dev_queue_xmit() to the bridge ports (port3, port4,
> > port5), ports which are DSA, so they do dev_queue_xmit() through their
> > DSA master - eth0. So the system behaves as instructed.
> 
> Yep. As i said in another email, consider eth1 being connected to an
> external managed switch. br1 is how you manage that switch, but that
> is all you use br1 for. eth1 is where you do networking.

It would have been good to have support for subtractive device tree
overlays, such that when there are multiple CPU ports in the device
tree, the stable device tree has both CPU ports marked with the
"ethernet" phandle, but the user has the option of deleting that
property from one of the CPU ports, turning it into a user port.
Currently for LS1028A I am doing this device tree post-processing
from the U-Boot command line:

=> tftp $fdt_addr_r ls1028/fsl-ls1028a-rdb.dtb
=> fdt addr $fdt_addr_r
=> fdt rm /soc/pcie@1f0000000/ethernet-switch@0,5/ports/port@4 ethernet

but it has the disadvantage that you can only operate with the
configuration that you booted with.

I analyzed the possibility for DSA to dynamically switch a port between
operating as a CPU port or a user port, but it is simply insanely complicated.