From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA9E9C6FD1D for ; Fri, 7 Apr 2023 13:48:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230194AbjDGNsr (ORCPT ); Fri, 7 Apr 2023 09:48:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231278AbjDGNsT (ORCPT ); Fri, 7 Apr 2023 09:48:19 -0400 Received: from mail-yw1-x112d.google.com (mail-yw1-x112d.google.com [IPv6:2607:f8b0:4864:20::112d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70ACCBB93; Fri, 7 Apr 2023 06:46:43 -0700 (PDT) Received: by mail-yw1-x112d.google.com with SMTP id 00721157ae682-5416698e889so797278027b3.2; Fri, 07 Apr 2023 06:46:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680875200; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cmc6uDj21KTxpfnQHdrxi7S8XMD1Ra3TJ9amtU9lpl8=; b=hF1TWDzIxiuMZgpm32X8C0WIN6cWULhfYL7uroZwTcImEqqBfdZtHnjv4AJTLVk8iW jv+iO7qu2ntN6s2VjCq5LKYOtTT8inK7fel6Rvit/p6/8vkIaM5ZWV1CUCpFvdFXOd9l vZQDKB4S7Qof/JZq4IjRlhqUoTS/DAkxODdmKXGvEBv/4hJAYfrYvklCcuPDuyMa+1ZO 2tI509BOwyARz35vsuzWrMtg4qj8J7V90nIhZLhBGNMG9rlmeuwcGqX9sUW9/zIAQxiO BaybGMG2ShzQV5jrgzvYqVWzX6K9pn789/x78Geyz1dkg+QFaQ29WSeDXGy1z0Gxu64d MPOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680875200; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cmc6uDj21KTxpfnQHdrxi7S8XMD1Ra3TJ9amtU9lpl8=; b=lIYblxSzyIGWo+caTqyJHAfmpNTEJA7Fa6wedDllG3nHMriw+PL0l7Px0nLKBjqXem LgrIB094RBoGcqUSZ6V/w9omZ0MOJ5Jw3MU8K5dyxIC+sYMs9QUwRBojOkJI9VYjBEFC Xh3BdGAjMEb8OIYWyhKaJOOAOZoL04bCOM8/JNGI6l7nB0aVv9mHN8XFkl0zp29uBv4R QlRlr1BVKYNy/75iiVwLgfUsEqlqN60aE4cFqTnJWoYl6qm80XaW749h2XXcIo+yREUu 2DAaHSOHqPnMpEUtvaJApxtpvoah3lWtWOwaQrrfBZ4SY6U1RqOJtiFBDeIFrek/zFJ3 LMvQ== X-Gm-Message-State: AAQBX9cM6HmIU1RJFKItsKDQq0qCYcGiON1qN4FzlwxusRc6qLh1YMjN egVaEun326c62WbHRVGgtW8= X-Google-Smtp-Source: AKy350ZFzcKKiizE3mygY5mbwu+iWhc2CY53VYCHnVhZoKnh3UBoK4RDgHLYO8R639CYYDemrvqkdA== X-Received: by 2002:a81:6906:0:b0:54e:d7f3:2be0 with SMTP id e6-20020a816906000000b0054ed7f32be0mr373767ywc.12.1680875199904; Fri, 07 Apr 2023 06:46:39 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id 139-20020a810e91000000b00545a0818473sm1034317ywo.3.2023.04.07.06.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 06:46:39 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH v2 net-next 01/14] net: dsa: mt7530: fix comments regarding port 5 and 6 for both switches Date: Fri, 7 Apr 2023 16:46:13 +0300 Message-Id: <20230407134626.47928-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230407134626.47928-1-arinc.unal@arinc9.com> References: <20230407134626.47928-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Arınç ÜNAL There's no logic to numerically order the CPU ports. State the port number and its being a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for both the MT7530 and MT7531 switches but there's no phy muxing on MT7531. These comments were gradually introduced with the commits below. ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") 38f790a80560 ("net: dsa: mt7530: Add support for port 5") 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware") c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index e4bb5037d352..31ef70f0cd12 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2506,7 +2506,7 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, a CPU port, supports rgmii, mii, and gmii. */ phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2514,7 +2514,7 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 6: /* 1st cpu port */ + case 6: /* Port 6, a CPU port, supports rgmii and trgmii. */ __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2539,14 +2539,14 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + case 5: /* Port 5, a CPU port, supports rgmii and sgmii/802.3z. */ if (mt7531_is_rgmii_port(priv, port)) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; - case 6: /* 1st cpu port supports sgmii/8023z only */ + case 6: /* Port 6, a CPU port, supports sgmii/802.3z only. */ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2738,7 +2738,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, state->interface != PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, a CPU port. */ if (priv->p5_interface == state->interface) break; @@ -2748,7 +2748,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (priv->p5_intf_sel != P5_DISABLED) priv->p5_interface = state->interface; break; - case 6: /* 1st cpu port */ + case 6: /* Port 6, a CPU port. */ if (priv->p6_interface == state->interface) break; -- 2.37.2