From: Vladimir Oltean <vladimir.oltean@nxp.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: shawnguo@kernel.org, s.hauer@pengutronix.de,
Russell King <rmk+kernel@armlinux.org.uk>,
arm-soc <arm@kernel.org>, netdev <netdev@vger.kernel.org>
Subject: Re: [PATCH 1/3] ARM: dts: imx51: ZII: Add missing phy-mode
Date: Fri, 7 Apr 2023 18:41:59 +0300 [thread overview]
Message-ID: <20230407154159.upribliycphlol5u@skbuf> (raw)
In-Reply-To: <20230407152503.2320741-2-andrew@lunn.ch>
On Fri, Apr 07, 2023 at 05:25:01PM +0200, Andrew Lunn wrote:
> The DSA framework has got more picky about always having a phy-mode
> for the CPU port. The imx51 Ethernet supports MII, and RMII. Set the
> switch phy-mode based on how the SoC Ethernet port has been
> configured.
>
> Additionally, the cpu label has never actually been used in the
> binding, so remove it.
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
In theory, an MII MAC-to-MAC connection should have phy-mode = "mii" on
one end and phy-mode = "rev-mii" on the other, right?
next prev parent reply other threads:[~2023-04-07 15:42 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-07 15:25 [PATCH 0/3] Add missing DSA properties for marvell switches Andrew Lunn
2023-04-07 15:25 ` [PATCH 1/3] ARM: dts: imx51: ZII: Add missing phy-mode Andrew Lunn
2023-04-07 15:41 ` Vladimir Oltean [this message]
2023-04-07 16:10 ` Andrew Lunn
2023-04-07 16:50 ` Vladimir Oltean
2023-04-07 17:06 ` Andrew Lunn
2023-04-10 10:00 ` Vladimir Oltean
2023-04-10 10:37 ` Russell King (Oracle)
2023-04-10 15:24 ` Vladimir Oltean
2023-04-10 11:59 ` Andrew Lunn
2023-04-10 12:35 ` Andrew Lunn
2023-04-10 13:11 ` Vladimir Oltean
2023-04-10 14:56 ` Andrew Lunn
2023-04-07 15:25 ` [PATCH 2/3] ARM: dts: imx6qdl: Add missing phy-mode and fixed links Andrew Lunn
2023-04-07 15:25 ` [PATCH 3/3] ARM64: dts: freescale: ZII: Add missing phy-mode Andrew Lunn
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