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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:00 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 05/30] net: dsa: mt7530: read XTAL value from correct register Date: Mon, 22 May 2023 15:15:07 +0300 Message-Id: <20230522121532.86610-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Arınç ÜNAL On commit 7ef6f6f8d237 ("net: dsa: mt7530: Add MT7621 TRGMII mode support") macros for reading the crystal frequency were added under the MT7530_HWTRAP register. However, the value given to the xtal variable on mt7530_pad_clk_setup() is read from the MT7530_MHWTRAP register instead. Although the document MT7621 Giga Switch Programming Guide v0.3 states that the value can be read from both registers, use the register where the macros were defined under. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b28d66a7c0b2..1a842d6fbc27 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -406,7 +406,7 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) struct mt7530_priv *priv = ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; - xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; + xtal = mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; if (xtal == HWTRAP_XTAL_20MHZ) { dev_err(priv->dev, -- 2.39.2