From: Stefan Eichenberger <eichest@gmail.com>
To: netdev@vger.kernel.org, andrew@lunn.ch, hkallweit1@gmail.com,
linux@armlinux.org.uk
Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
pabeni@redhat.com, francesco.dolcini@toradex.com
Subject: [PATCH v1 1/2] net: phy: add the link modes for 1000BASE-T1 Ethernet PHY
Date: Mon, 3 Jul 2023 14:44:39 +0200 [thread overview]
Message-ID: <20230703124440.391970-2-eichest@gmail.com> (raw)
In-Reply-To: <20230703124440.391970-1-eichest@gmail.com>
This patch adds the link modes for the 1000BASE-T1 Ethernet PHYs. It
supports 100BASE-T1/1000BASE-T1 in full duplex mode. So far I could not
find a 1000BASE-T1 PHY that also supports 10BASE-T1, so this mode is not
added.
Signed-off-by: Stefan Eichenberger <eichest@gmail.com>
---
drivers/net/phy/phy_device.c | 14 ++++++++++++++
include/linux/phy.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 17d0d0555a79f..4492dbd525f4f 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -50,6 +50,9 @@ EXPORT_SYMBOL_GPL(phy_basic_t1_features);
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;
EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features);
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_t1_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_t1_features);
+
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
EXPORT_SYMBOL_GPL(phy_gbit_features);
@@ -109,6 +112,13 @@ const int phy_basic_t1s_p2mp_features_array[2] = {
};
EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features_array);
+const int phy_gbit_t1_features_array[3] = {
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
+ ETHTOOL_LINK_MODE_1000baseT1_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_gbit_t1_features_array);
+
const int phy_gbit_features_array[2] = {
ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
@@ -165,6 +175,10 @@ static void features_init(void)
linkmode_set_bit_array(phy_basic_t1s_p2mp_features_array,
ARRAY_SIZE(phy_basic_t1s_p2mp_features_array),
phy_basic_t1s_p2mp_features);
+ /* 1000 full, TP */
+ linkmode_set_bit_array(phy_gbit_t1_features_array,
+ ARRAY_SIZE(phy_gbit_t1_features_array),
+ phy_gbit_t1_features);
/* 10/100 half/full + 1000 half/full */
linkmode_set_bit_array(phy_basic_ports_array,
diff --git a/include/linux/phy.h b/include/linux/phy.h
index c5a0dc829714f..81b6731a85a86 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -47,6 +47,7 @@
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;
+extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_t1_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
@@ -58,6 +59,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;
#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
#define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features)
+#define PHY_GBIT_T1_FEATURES ((unsigned long *)&phy_gbit_t1_features)
#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
--
2.39.2
next prev parent reply other threads:[~2023-07-03 12:44 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-03 12:44 [PATCH v1 0/2] Add a driver for the Marvell 88Q2110 PHY Stefan Eichenberger
2023-07-03 12:44 ` Stefan Eichenberger [this message]
2023-07-03 12:44 ` [PATCH v1 2/2] net: phy: marvell-88q2xxx: add " Stefan Eichenberger
2023-07-03 13:46 ` Andrew Lunn
2023-07-03 15:17 ` Francesco Dolcini
2023-07-03 15:27 ` Francesco Dolcini
2023-07-13 6:31 ` Russell King (Oracle)
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