From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B761E57C for ; Wed, 26 Jul 2023 15:24:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8ED6C433C7; Wed, 26 Jul 2023 15:24:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690385081; bh=XtQHPjwlUAYxGYo7V7WNdtEo+xDINh3xf8oWKZdFtPM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ajWOBzMzGhBoqzfc5/DW9aF/gzYa0wM+vSx2pxzmI/7dY0miIeIIjqjyBGxE0JzWb 0+Be9ZPNi4QMYnzvKxNL06mLMrPnlHI6r1AFOiBDJf0fub79NUx64XIhQxnbfb0qAS 0D2Qj+MXNiJeESeORBdztPo+ffbinai/Z+J5lIIuGm3cxF998g2HPKBJc4e4AKgdHr SWC1FzJ4EbDQNDK/SsYHmtcsCxrAyNLRVB7/n0Be8lW9ED2pkKPxE56jwkFYjX1z3x FdGILD3G7swQqW17sCU6lryDnJAMjG5uHjqnHSQ90YgI369/OKpvKUMfyTRSF281Do G3Z8h4PW665iA== Received: (nullmailer pid 1474009 invoked by uid 1000); Wed, 26 Jul 2023 15:24:39 -0000 Date: Wed, 26 Jul 2023 09:24:39 -0600 From: Rob Herring To: Jisheng Zhang Cc: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH net-next 09/10] dt-bindings: net: snps,dwmac: add per channel irq support Message-ID: <20230726152439.GA1471409-robh@kernel.org> References: <20230723161029.1345-1-jszhang@kernel.org> <20230723161029.1345-10-jszhang@kernel.org> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230723161029.1345-10-jszhang@kernel.org> On Mon, Jul 24, 2023 at 12:10:28AM +0800, Jisheng Zhang wrote: > The IP supports per channel interrupt, add support for this usage case. > > Signed-off-by: Jisheng Zhang > --- > .../devicetree/bindings/net/snps,dwmac.yaml | 23 +++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > index bb80ca205d26..525210c2c06c 100644 > --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml > +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > @@ -101,6 +101,11 @@ properties: > minItems: 1 > maxItems: 2 > > + snps,per-channel-interrupt: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Indicates that Rx and Tx complete will generate a unique interrupt for each channel Can't you determine this based on the number of interrupts or interrupt names? > + > interrupts: > minItems: 1 > items: > @@ -109,6 +114,8 @@ properties: > - description: The interrupt that occurs when Rx exits the LPI state > - description: The interrupt that occurs when Safety Feature Correctible Errors happen > - description: The interrupt that occurs when Safety Feature Uncorrectible Errors happen > + - description: All of the rx per-channel interrupts > + - description: All of the tx per-channel interrupts You added 2 interrupts here and... > > interrupt-names: > minItems: 1 > @@ -118,6 +125,22 @@ properties: > - const: eth_lpi > - const: sfty_ce_irq > - const: sfty_ue_irq > + - const: rx0 > + - const: rx1 > + - const: rx2 > + - const: rx3 > + - const: rx4 > + - const: rx5 > + - const: rx6 > + - const: rx7 > + - const: tx0 > + - const: tx1 > + - const: tx2 > + - const: tx3 > + - const: tx4 > + - const: tx5 > + - const: tx6 > + - const: tx7 And 16 here? > > clocks: > minItems: 1 > -- > 2.40.1 >