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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org Subject: Re: [PATCH net-next] net: dsa: mark parsed interface mode for legacy switch drivers Message-ID: <20230817182729.q6rf327t7dfzxiow@skbuf> References: <20230808135215.tqhw4mmfwp2c3zy2@skbuf> <20230810151617.wv5xt5idbfu7wkyn@skbuf> <20230814145948.u6ul5dgjpl5bnasp@skbuf> <055be6c4-3c28-459d-bb52-5ac2ee24f1f1@lunn.ch> <8687110a-5ce8-474c-8c20-ca682a98a94c@lunn.ch> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8687110a-5ce8-474c-8c20-ca682a98a94c@lunn.ch> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On Mon, Aug 14, 2023 at 07:05:19PM +0200, Andrew Lunn wrote: > arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts: > switch0port5: port@5 { > reg = <5>; > label = "dsa"; > phy-mode = "rgmii-txid"; > link = <&switch1port6 > &switch2port9>; > fixed-link { > speed = <1000>; > full-duplex; > }; > }; > > and the other end of this link: > > switch1port6: port@6 { > reg = <6>; > label = "dsa"; > phy-mode = "rgmii-txid"; > link = <&switch0port5>; > fixed-link { > speed = <1000>; > full-duplex; > }; > }; > > imx7d-zii-rpu2.dts: > port@5 { > reg = <5>; > label = "cpu"; > ethernet = <&fec1>; > phy-mode = "rgmii-id"; > > fixed-link { > speed = <1000>; > full-duplex; > }; > }; > > With the 'cpu' case, it is clearly acting like a PHY to the SoCs MAC, > so it does not seem too unreasonable for it to act upon it. For a DSA > link there is not a clear MAC-PHY relationship, but we do somehow need > to specify delays. Andrew, I'd argue that the MAC-PHY relationship between the DSA master and the CPU port is equally clear as between 2 arbitrary cascade ports. Which is: not clear at all. The RGMII standard does not talk about the existence of a MAC role and a PHY role, to my knowledge. These are 2 MACs back to back, in both cases. With rx-internal-delay-ps and tx-internal-delay-ps in each MAC node, you get the freedom of specifying RGMII delays in whichever way is needed, without baking in any assumption that the port plays the role of a PHY or not.