* [PATCH net] net: ethernet: mtk_eth_soc: add reset bits for MT7988
@ 2023-08-18 18:15 Daniel Golle
2023-08-19 14:41 ` Simon Horman
2023-08-21 18:38 ` kernel test robot
0 siblings, 2 replies; 3+ messages in thread
From: Daniel Golle @ 2023-08-18 18:15 UTC (permalink / raw)
To: Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Matthias Brugger, AngeloGioacchino Del Regno,
Daniel Golle, netdev, linux-kernel, linux-arm-kernel,
linux-mediatek
Add bits needed to reset the frame engine on MT7988.
Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 76 +++++++++++++++------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++-
2 files changed, 64 insertions(+), 23 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index fe05c90202699..2482f47313085 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3613,19 +3613,34 @@ static void mtk_hw_reset(struct mtk_eth *eth)
{
u32 val;
- if (mtk_is_netsys_v2_or_greater(eth)) {
+ if (mtk_is_netsys_v2_or_greater(eth))
regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
+
+ if (mtk_is_netsys_v3_or_greater(eth)) {
+ val = RSTCTRL_PPE0_V3;
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+ val |= RSTCTRL_PPE1_V3;
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
+ val |= RSTCTRL_PPE2;
+
+ val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
+ } else if (mtk_is_netsys_v2_or_greater(eth)) {
val = RSTCTRL_PPE0_V2;
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+ val |= RSTCTRL_PPE1;
} else {
val = RSTCTRL_PPE0;
}
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
- val |= RSTCTRL_PPE1;
-
ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
- if (mtk_is_netsys_v2_or_greater(eth))
+ if (mtk_is_netsys_v3_or_greater(eth))
+ regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
+ 0x6f8ff);
+ else if (mtk_is_netsys_v2_or_greater(eth))
regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
0x3ffffff);
}
@@ -3651,13 +3666,21 @@ static void mtk_hw_warm_reset(struct mtk_eth *eth)
return;
}
- if (mtk_is_netsys_v2_or_greater(eth))
+ if (mtk_is_netsys_v3_or_greater(eth)) {
+ rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+ rst_mask |= RSTCTRL_PPE1_V3;
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
+ rst_mask |= RSTCTRL_PPE2;
+
+ rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
+ } else if (mtk_is_netsys_v2_or_greater(eth)) {
rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
- else
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+ rst_mask |= RSTCTRL_PPE1;
+ } else {
rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
-
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
- rst_mask |= RSTCTRL_PPE1;
+ }
regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
@@ -4009,11 +4032,17 @@ static void mtk_prepare_for_reset(struct mtk_eth *eth)
u32 val;
int i;
- /* disabe FE P3 and P4 */
- val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3;
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
- val |= MTK_FE_LINK_DOWN_P4;
- mtk_w32(eth, val, MTK_FE_GLO_CFG);
+ /* set FE PPE ports link down */
+ for (i = MTK_GMAC1_ID;
+ i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
+ i += 2) {
+ val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+ val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
+ val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
+ mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
+ }
/* adjust PPE configurations to prepare for reset */
for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
@@ -4074,11 +4103,18 @@ static void mtk_pending_work(struct work_struct *work)
}
}
- /* enabe FE P3 and P4 */
- val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3;
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
- val &= ~MTK_FE_LINK_DOWN_P4;
- mtk_w32(eth, val, MTK_FE_GLO_CFG);
+ /* set FE PPE ports link up */
+ for (i = MTK_GMAC1_ID;
+ i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
+ i += 2) {
+ val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+ val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
+ val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
+
+ mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
+ }
clear_bit(MTK_RESETTING, ð->state);
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 8d2d35b322351..bb4313c92fae0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -76,9 +76,8 @@
#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
/* Frame Engine Global Configuration */
-#define MTK_FE_GLO_CFG 0x00
-#define MTK_FE_LINK_DOWN_P3 BIT(11)
-#define MTK_FE_LINK_DOWN_P4 BIT(12)
+#define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
+#define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16)
/* Frame Engine Global Reset Register */
#define MTK_RST_GL 0x04
@@ -522,9 +521,15 @@
/* ethernet reset control register */
#define ETHSYS_RSTCTRL 0x34
#define RSTCTRL_FE BIT(6)
+#define RSTCTRL_WDMA0 BIT(24)
+#define RSTCTRL_WDMA1 BIT(25)
+#define RSTCTRL_WDMA2 BIT(26)
#define RSTCTRL_PPE0 BIT(31)
#define RSTCTRL_PPE0_V2 BIT(30)
#define RSTCTRL_PPE1 BIT(31)
+#define RSTCTRL_PPE0_V3 BIT(29)
+#define RSTCTRL_PPE1_V3 BIT(30)
+#define RSTCTRL_PPE2 BIT(31)
#define RSTCTRL_ETH BIT(23)
/* ethernet reset check idle register */
--
2.41.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH net] net: ethernet: mtk_eth_soc: add reset bits for MT7988
2023-08-18 18:15 [PATCH net] net: ethernet: mtk_eth_soc: add reset bits for MT7988 Daniel Golle
@ 2023-08-19 14:41 ` Simon Horman
2023-08-21 18:38 ` kernel test robot
1 sibling, 0 replies; 3+ messages in thread
From: Simon Horman @ 2023-08-19 14:41 UTC (permalink / raw)
To: Daniel Golle
Cc: Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Matthias Brugger, AngeloGioacchino Del Regno, netdev,
linux-kernel, linux-arm-kernel, linux-mediatek
On Fri, Aug 18, 2023 at 07:15:24PM +0100, Daniel Golle wrote:
> Add bits needed to reset the frame engine on MT7988.
>
> Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
> drivers/net/ethernet/mediatek/mtk_eth_soc.c | 76 +++++++++++++++------
> drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++-
> 2 files changed, 64 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> index fe05c90202699..2482f47313085 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> @@ -3613,19 +3613,34 @@ static void mtk_hw_reset(struct mtk_eth *eth)
> {
> u32 val;
>
> - if (mtk_is_netsys_v2_or_greater(eth)) {
> + if (mtk_is_netsys_v2_or_greater(eth))
> regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
> +
> + if (mtk_is_netsys_v3_or_greater(eth)) {
> + val = RSTCTRL_PPE0_V3;
> +
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> + val |= RSTCTRL_PPE1_V3;
> +
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
> + val |= RSTCTRL_PPE2;
> +
> + val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
> + } else if (mtk_is_netsys_v2_or_greater(eth)) {
> val = RSTCTRL_PPE0_V2;
> +
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> + val |= RSTCTRL_PPE1;
> } else {
> val = RSTCTRL_PPE0;
> }
>
> - if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> - val |= RSTCTRL_PPE1;
> -
> ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
>
> - if (mtk_is_netsys_v2_or_greater(eth))
> + if (mtk_is_netsys_v3_or_greater(eth))
> + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
> + 0x6f8ff);
> + else if (mtk_is_netsys_v2_or_greater(eth))
> regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
> 0x3ffffff);
> }
> @@ -3651,13 +3666,21 @@ static void mtk_hw_warm_reset(struct mtk_eth *eth)
> return;
> }
>
> - if (mtk_is_netsys_v2_or_greater(eth))
> + if (mtk_is_netsys_v3_or_greater(eth)) {
> + rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> + rst_mask |= RSTCTRL_PPE1_V3;
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
> + rst_mask |= RSTCTRL_PPE2;
> +
> + rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
> + } else if (mtk_is_netsys_v2_or_greater(eth)) {
> rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
> - else
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> + rst_mask |= RSTCTRL_PPE1;
> + } else {
> rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
> -
> - if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
> - rst_mask |= RSTCTRL_PPE1;
> + }
>
> regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
>
Hi Daniel,
The bits set by the code in the above two hunks seem both complex
and similar. At the risk of suggesting excessive complexity,
I do wonder if they can be consolidated somehow.
Maybe the approach you have taken is best as a fix for net.
But a follow-up could be considered for net-next.
Just an idea.
...
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH net] net: ethernet: mtk_eth_soc: add reset bits for MT7988
2023-08-18 18:15 [PATCH net] net: ethernet: mtk_eth_soc: add reset bits for MT7988 Daniel Golle
2023-08-19 14:41 ` Simon Horman
@ 2023-08-21 18:38 ` kernel test robot
1 sibling, 0 replies; 3+ messages in thread
From: kernel test robot @ 2023-08-21 18:38 UTC (permalink / raw)
To: Daniel Golle, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Matthias Brugger, AngeloGioacchino Del Regno,
linux-kernel, linux-arm-kernel, linux-mediatek
Cc: oe-kbuild-all, netdev
Hi Daniel,
kernel test robot noticed the following build errors:
[auto build test ERROR on linux-next/master]
[cannot apply to net/main linus/master v6.5-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988/20230821-102205
base: linux-next/master
patch link: https://lore.kernel.org/r/b983a3adf5184a30e4ce620fbbf028c9c76648ae.1692382239.git.daniel%40makrotopia.org
patch subject: [PATCH net] net: ethernet: mtk_eth_soc: add reset bits for MT7988
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20230822/202308220205.gbt5lcAY-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230822/202308220205.gbt5lcAY-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202308220205.gbt5lcAY-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/net/ethernet/mediatek/mtk_eth_soc.c:31:
drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function 'mtk_hw_reset':
>> drivers/net/ethernet/mediatek/mtk_eth_soc.c:3625:50: error: 'MTK_RSTCTRL_PPE2' undeclared (first use in this function); did you mean 'MTK_RSTCTRL_PPE1'?
3625 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/mediatek/mtk_eth_soc.h:1022:53: note: in definition of macro 'MTK_HAS_CAPS'
1022 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
| ^~
drivers/net/ethernet/mediatek/mtk_eth_soc.c:3625:50: note: each undeclared identifier is reported only once for each function it appears in
3625 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/mediatek/mtk_eth_soc.h:1022:53: note: in definition of macro 'MTK_HAS_CAPS'
1022 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
| ^~
drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function 'mtk_hw_warm_reset':
drivers/net/ethernet/mediatek/mtk_eth_soc.c:3673:50: error: 'MTK_RSTCTRL_PPE2' undeclared (first use in this function); did you mean 'MTK_RSTCTRL_PPE1'?
3673 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/mediatek/mtk_eth_soc.h:1022:53: note: in definition of macro 'MTK_HAS_CAPS'
1022 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
| ^~
drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function 'mtk_prepare_for_reset':
drivers/net/ethernet/mediatek/mtk_eth_soc.c:4042:50: error: 'MTK_RSTCTRL_PPE2' undeclared (first use in this function); did you mean 'MTK_RSTCTRL_PPE1'?
4042 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/mediatek/mtk_eth_soc.h:1022:53: note: in definition of macro 'MTK_HAS_CAPS'
1022 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
| ^~
drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function 'mtk_pending_work':
drivers/net/ethernet/mediatek/mtk_eth_soc.c:4113:50: error: 'MTK_RSTCTRL_PPE2' undeclared (first use in this function); did you mean 'MTK_RSTCTRL_PPE1'?
4113 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
| ^~~~~~~~~~~~~~~~
drivers/net/ethernet/mediatek/mtk_eth_soc.h:1022:53: note: in definition of macro 'MTK_HAS_CAPS'
1022 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
| ^~
vim +3625 drivers/net/ethernet/mediatek/mtk_eth_soc.c
3611
3612 static void mtk_hw_reset(struct mtk_eth *eth)
3613 {
3614 u32 val;
3615
3616 if (mtk_is_netsys_v2_or_greater(eth))
3617 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
3618
3619 if (mtk_is_netsys_v3_or_greater(eth)) {
3620 val = RSTCTRL_PPE0_V3;
3621
3622 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3623 val |= RSTCTRL_PPE1_V3;
3624
> 3625 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3626 val |= RSTCTRL_PPE2;
3627
3628 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3629 } else if (mtk_is_netsys_v2_or_greater(eth)) {
3630 val = RSTCTRL_PPE0_V2;
3631
3632 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3633 val |= RSTCTRL_PPE1;
3634 } else {
3635 val = RSTCTRL_PPE0;
3636 }
3637
3638 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
3639
3640 if (mtk_is_netsys_v3_or_greater(eth))
3641 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3642 0x6f8ff);
3643 else if (mtk_is_netsys_v2_or_greater(eth))
3644 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3645 0x3ffffff);
3646 }
3647
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-08-21 19:01 UTC | newest]
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2023-08-18 18:15 [PATCH net] net: ethernet: mtk_eth_soc: add reset bits for MT7988 Daniel Golle
2023-08-19 14:41 ` Simon Horman
2023-08-21 18:38 ` kernel test robot
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