From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A7262628D; Mon, 18 Sep 2023 18:13:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9611C433C8; Mon, 18 Sep 2023 18:13:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695060808; bh=rQ7ojhg05dRv+DYjdzxtwP35g4EgY5jql6tHXuMTQJ8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=A9MTYIWeX6qk/C2NyyQZJsGmkblO+CavtmKS3/LkcoyVDKlKm3UMpqXWtKQVjPSPh P9SGB8nAeDA3/TdvpUYDo8iyArokxssFSU2zhYissgl4C3jsYBjoAIs2kNHyzI3uKJ dLERPpgiGV576S3L9yGF0jfUINiS6a40lLYn5CdayIZk+07/4oE3a12w64ku9VKiO1 ndQ4U9jqJCHjN/krZ8vPEGLpkPVlYC/1fdSm6IF6h2Y5T+nWNrVLKjFRl5hn92NDW5 XipP+Vnp8GULgxTMvZHToE/3q0oSMZdoXAhA3FnqDgWD2crGb330IFlahMlm9BunKr SxwrcGcWJz5ew== Received: (nullmailer pid 1463138 invoked by uid 1000); Mon, 18 Sep 2023 18:13:19 -0000 Date: Mon, 18 Sep 2023 13:13:19 -0500 From: Rob Herring To: =?utf-8?B?QXLEsW7DpyDDnE5BTA==?= Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Krzysztof Kozlowski , Conor Dooley , George McCollister , Andrew Lunn , Florian Fainelli , Vladimir Oltean , Kurt Kanzenbach , Matthias Brugger , AngeloGioacchino Del Regno , Woojung Huh , UNGLinuxDriver@microchip.com, Linus Walleij , Alvin =?utf-8?Q?=C5=A0ipraga?= , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Marcin Wojtas , "Russell King (Oracle)" , Lars Povlsen , Steen Hegelund , Daniel Machon , Radhey Shyam Pandey , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Geert Uytterhoeven , Magnus Damm , Maxime Chevallier , Nicolas Ferre , Claudiu Beznea , Marek Vasut , Claudiu Manoil , Alexandre Belloni , John Crispin , Madalin Bucur , Ioana Ciornei , Lorenzo Bianconi , Felix Fietkau , Horatiu Vultur , Oleksij Rempel , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Grygorii Strashko , Sekhar Nori , Shyam Pandey , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH net-next v2 07/10] dt-bindings: net: enforce phylink bindings on certain ethernet controllers Message-ID: <20230918181319.GA1445647-robh@kernel.org> References: <20230916110902.234273-1-arinc.unal@arinc9.com> <20230916110902.234273-8-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230916110902.234273-8-arinc.unal@arinc9.com> On Sat, Sep 16, 2023 at 02:08:59PM +0300, Arınç ÜNAL wrote: > Phylink bindings are required for ethernet controllers that utilise > phylink_fwnode_phy_connect() directly or through phylink_of_phy_connect(), > and register OF-based only MDIO buses, if they register any. What is phylink? Don't describe/justify binding changes based on some Linux functions. > All the drivers that utilise phylink_fwnode_phy_connect() directly or > through phylink_of_phy_connect(): > > - DSA > - drivers/net/ethernet/mscc/ocelot_net.c > - mscc,vsc7514-switch.yaml > - drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c > - microchip,sparx5-switch.yaml > - drivers/net/ethernet/altera/altera_tse_main.c > - altr,tse.yaml > - drivers/net/ethernet/xilinx/xilinx_axienet_main.c > - xlnx,axi-ethernet.yaml > - drivers/net/ethernet/mediatek/mtk_eth_soc.c > - mediatek,net.yaml > - drivers/net/ethernet/ti/am65-cpsw-nuss.c > - ti,k3-am654-cpsw-nuss.yaml > - drivers/net/ethernet/atheros/ag71xx.c > - qca,ar71xx.yaml > - drivers/net/ethernet/freescale/dpaa/dpaa_eth.c > - fsl,fman-dtsec.yaml > - drivers/net/ethernet/microchip/lan966x/lan966x_main.c > - microchip,lan966x-switch.yaml > - drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > - marvell,pp2.yaml > - drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c > - fsl,qoriq-mc-dpmac.yaml > - drivers/net/ethernet/cadence/macb_main.c > - cdns,macb.yaml > - Can register non-OF-based bus. > - drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > - snps,dwmac.yaml > - Can register non-OF-based bus. > - drivers/net/ethernet/marvell/mvneta.c > - marvell-armada-370-neta.txt > - drivers/net/ethernet/freescale/enetc/enetc.c > - fsl-enetc.txt > > RFC: The drivers marked with "can register non-OF-based bus" seem to search > the MDIO bus to connect the PHY to the MAC using phylink_connect_phy() > and/or phy_find_first() if phylink bindings don't exist. Should we enforce > phylink bindings on their schemas regardless? Generally, describing the MDIO bus in DT is optional because the devices on the bus can be discovered. But then sometimes a device can't be discovered or has additional properties which aren't discoverable. So in general, an MDIO bus in DT should always be optional, but always supported (and validated) if present. If the device has a separate node for the MDIO controller (i.e. one with a compatible and reg for the MDIO controller register), then that should always be there (because the h/w is always there). Rob