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From: Pu Lehui <pulehui@huaweicloud.com>
To: bpf@vger.kernel.org, linux-riscv@lists.infradead.org,
	netdev@vger.kernel.org
Cc: "Björn Töpel" <bjorn@kernel.org>,
	"Alexei Starovoitov" <ast@kernel.org>,
	"Daniel Borkmann" <daniel@iogearbox.net>,
	"Andrii Nakryiko" <andrii@kernel.org>,
	"Martin KaFai Lau" <martin.lau@linux.dev>,
	"Song Liu" <song@kernel.org>, "Yonghong Song" <yhs@fb.com>,
	"John Fastabend" <john.fastabend@gmail.com>,
	"KP Singh" <kpsingh@kernel.org>,
	"Stanislav Fomichev" <sdf@google.com>,
	"Hao Luo" <haoluo@google.com>, "Jiri Olsa" <jolsa@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Conor Dooley" <conor@kernel.org>,
	"Luke Nelson" <luke.r.nels@gmail.com>,
	"Pu Lehui" <pulehui@huawei.com>,
	"Pu Lehui" <pulehui@huaweicloud.com>
Subject: [PATCH bpf-next v2 1/6] riscv, bpf: Unify 32-bit sign-extension to emit_sextw
Date: Tue, 19 Sep 2023 11:58:34 +0800	[thread overview]
Message-ID: <20230919035839.3297328-2-pulehui@huaweicloud.com> (raw)
In-Reply-To: <20230919035839.3297328-1-pulehui@huaweicloud.com>

From: Pu Lehui <pulehui@huawei.com>

For code unification, add emit_sextw wrapper to unify all the 32-bit
sign-extension operations.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
---
 arch/riscv/net/bpf_jit.h        |  5 +++++
 arch/riscv/net/bpf_jit_comp64.c | 10 +++++-----
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index d21c6c92a..03a6ecb43 100644
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -1084,6 +1084,11 @@ static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
 		emit(rv_subw(rd, rs1, rs2), ctx);
 }
 
+static inline void emit_sextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
+{
+	emit_addiw(rd, rs, 0, ctx);
+}
+
 #endif /* __riscv_xlen == 64 */
 
 void bpf_jit_build_prologue(struct rv_jit_context *ctx);
diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index 8423f4ddf..8b654c0cf 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -413,8 +413,8 @@ static void emit_zext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx)
 
 static void emit_sext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx)
 {
-	emit_addiw(RV_REG_T2, *rd, 0, ctx);
-	emit_addiw(RV_REG_T1, *rs, 0, ctx);
+	emit_sextw(RV_REG_T2, *rd, ctx);
+	emit_sextw(RV_REG_T1, *rs, ctx);
 	*rd = RV_REG_T2;
 	*rs = RV_REG_T1;
 }
@@ -429,7 +429,7 @@ static void emit_zext_32_rd_t1(u8 *rd, struct rv_jit_context *ctx)
 
 static void emit_sext_32_rd(u8 *rd, struct rv_jit_context *ctx)
 {
-	emit_addiw(RV_REG_T2, *rd, 0, ctx);
+	emit_sextw(RV_REG_T2, *rd, ctx);
 	*rd = RV_REG_T2;
 }
 
@@ -1057,7 +1057,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 			emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx);
 			break;
 		case 32:
-			emit_addiw(rd, rs, 0, ctx);
+			emit_sextw(rd, rs, ctx);
 			break;
 		}
 		if (!is64 && !aux->verifier_zext)
@@ -1457,7 +1457,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 		 * as t1 is used only in comparison against zero.
 		 */
 		if (!is64 && imm < 0)
-			emit_addiw(RV_REG_T1, RV_REG_T1, 0, ctx);
+			emit_sextw(RV_REG_T1, RV_REG_T1, ctx);
 		e = ctx->ninsns;
 		rvoff -= ninsns_rvoff(e - s);
 		emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx);
-- 
2.25.1


  reply	other threads:[~2023-09-19  3:58 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-19  3:58 [PATCH bpf-next v2 0/6] Zbb support and code simplification for RV64 JIT Pu Lehui
2023-09-19  3:58 ` Pu Lehui [this message]
2023-09-28 10:45   ` [PATCH bpf-next v2 1/6] riscv, bpf: Unify 32-bit sign-extension to emit_sextw Björn Töpel
2023-09-19  3:58 ` [PATCH bpf-next v2 2/6] riscv, bpf: Unify 32-bit zero-extension to emit_zextw Pu Lehui
2023-09-28 10:46   ` Björn Töpel
2023-09-19  3:58 ` [PATCH bpf-next v2 3/6] riscv, bpf: Simplify sext and zext logics in branch instructions Pu Lehui
2023-09-28 10:55   ` Björn Töpel
2023-09-19  3:58 ` [PATCH bpf-next v2 4/6] riscv, bpf: Add necessary Zbb instructions Pu Lehui
2023-09-19  7:38   ` Conor Dooley
2023-09-19  7:43     ` Pu Lehui
2023-09-28 11:02   ` Björn Töpel
2023-09-19  3:58 ` [PATCH bpf-next v2 5/6] riscv, bpf: Optimize sign-extention mov insns with Zbb support Pu Lehui
2023-09-28 11:04   ` Björn Töpel
2023-09-19  3:58 ` [PATCH bpf-next v2 6/6] riscv, bpf: Optimize bswap " Pu Lehui
2023-09-28 11:08   ` Björn Töpel
2024-01-15 12:26     ` Pu Lehui
2023-09-26 13:30 ` [PATCH bpf-next v2 0/6] Zbb support and code simplification for RV64 JIT Björn Töpel
2023-09-28 10:44 ` Björn Töpel
2024-01-15 12:22   ` Pu Lehui
2024-01-16  9:05     ` Björn Töpel

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