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Date: Thu, 9 Nov 2023 17:25:08 -0500
From: Simon Horman <horms@kernel.org>
To: Min Li <lnimi@hotmail.com>
Cc: richardcochran@gmail.com, lee@kernel.org, linux-kernel@vger.kernel.org,
	netdev@vger.kernel.org, Min Li <min.li.xe@renesas.com>
Subject: Re: [PATCH net-next v2 1/1] ptp: clockmatrix: support 32-bit address
 space
Message-ID: <20231109222508.GC568506@kernel.org>
References: <MW5PR03MB6932A4AAD4F612B45E9F6856A0AFA@MW5PR03MB6932.namprd03.prod.outlook.com>
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On Thu, Nov 09, 2023 at 01:13:52PM -0500, Min Li wrote:
> From: Min Li <min.li.xe@renesas.com>
> 
> We used to assume 0x2010xxxx address. Now that
> we need to access 0x2011xxxx address, we need
> to support read/write the whole 32-bit address space.
> 
> Signed-off-by: Min Li <min.li.xe@renesas.com>
> ---
> - Drop MAX_ABS_WRITE_PHASE_PICOSECONDS advised by Rahul

...

> @@ -62,7 +62,8 @@ static int contains_full_configuration(struct idtcm *idtcm,
>  				       const struct firmware *fw)
>  {
>  	struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
> -	u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
> +	u16 scratch = SCSR_ADDR(IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH));

Hi Min Li,

I think a similar conversion for scratch in idtcm_load_firmware()
is required.

As flagged by clang-16 W=1, and Smatch.
`
> +	u16 gpio_control = SCSR_ADDR(GPIO_USER_CONTROL);
>  	s32 full_count;
>  	s32 count = 0;
>  	u16 regaddr;

...