[PATCH net-next v2 1/8] dt-bindings: net: Introduce the Qualcomm IPQESS Ethernet switch

Romain Gantois
2023-11-14T09:08:13Z

Add the DT binding for the IPQESS Ethernet switch subsystem, that
integrates a modified QCA8K switch and an EDMA MAC controller. It inherits
from a basic ethernet switch binding and adds three regmaps, a phandle and
reset line for the PSGMII, a phandle to the MDIO bus, a clock, and 32
interrupts.

Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
---
.../bindings/net/qcom,ipq4019-ess.yaml | 152 ++++++++++++++++++
1 file changed, 152 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml

diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
new file mode 100644
index 000000000000..85dff85e50b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/qcom,ipq4019-ess.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ4019 Ethernet Switch Subsystem
+
+maintainers:
+ - Romain Gantois <romain.gantois@bootlin.com>
+
+$ref: ethernet-switch.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq4019-ess
+
+ reg:
+ items:
+ - description: Base ESS registers, which configure the integrated QCA8K switch.
+ - description: ESS PSGMII-related registers, which control VCO calibration and link
+ modes.
+ - description: ESS EDMA controller registers. The EDMA controller is an Ethernet
+ controller connected to the integrated switch's CPU port.
+ reg-names:
+ items:
+ - const: base
+ - const: psgmii_phy
+ - const: edma
+
+ resets:
+ items:
+ - description: Handle to the PSGMII reset line.
+ - description: Handle to the ESS reset line.
+
+ reset-names:
+ items:
+ - const: psgmii
+ - const: ess
+
+ clocks:
+ maxItems: 1
+ description: Handle to the GCC ESS clock
+
+ mdio:
+ maxItems: 1
+ description: Handle to the IPQ4019 MDIO Controller
+
+ interrupts:
+ maxItems: 32
+ description: One interrupt per tx and rx queue, the first 16 are rx queues
+ and the last 16 are the tx queues
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - resets
+ - reset-names
+ - clocks
+ - mdio
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ switch: switch@c000000 {
+ compatible = "qcom,ipq4019-ess";
+ reg = <0xc000000 0x80000>, <0x98000 0x800>, <0xc080000 0x80000>;
+ reg-names = "base", "psgmii_phy", "edma";
+ resets = <&gcc ESS_PSGMII_ARES>, <&gcc ESS_RESET>;
+ reset-names = "psgmii", "ess";
+ clocks = <&gcc GCC_ESS_CLK>;
+ mdio = <&mdio>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swport1: port@1 { /* MAC1 */
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <&ethphy0>;
+ phy-mode = "psgmii";
+ };
+
+ swport2: port@2 { /* MAC2 */
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&ethphy1>;
+ phy-mode = "psgmii";
+ };
+
+ swport3: port@3 { /* MAC3 */
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <&ethphy2>;
+ phy-mode = "psgmii";
+ };
+
+ swport4: port@4 { /* MAC4 */
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <&ethphy3>;
+ phy-mode = "psgmii";
+ };
+
+ swport5: port@5 { /* MAC5 */
+ reg = <5>;
+ label = "wan";
+ phy-handle = <&ethphy4>;
+ phy-mode = "psgmii";
+ };
+ };
+ };
+
+...
--
2.42.0